From f7cabdec391f1d65c4d4b1c24c3a24ac573cee1f Mon Sep 17 00:00:00 2001 From: jsg Date: Fri, 16 Sep 2022 02:29:47 +0000 Subject: [PATCH] drm/i915: Implement WaEdpLinkRateDataReload From Ville Syrjala d2ca79dd0b5487991dac52c6b679915dbd70ee4c in linux 5.15.y/5.15.68 672d6ca758651f0ec12cd0d59787067a5bde1c96 in mainline linux --- .../drm/i915/display/intel_dp_link_training.c | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/sys/dev/pci/drm/i915/display/intel_dp_link_training.c b/sys/dev/pci/drm/i915/display/intel_dp_link_training.c index 508a514c5e3..d77d91c0a03 100644 --- a/sys/dev/pci/drm/i915/display/intel_dp_link_training.c +++ b/sys/dev/pci/drm/i915/display/intel_dp_link_training.c @@ -475,6 +475,28 @@ intel_dp_prepare_link_train(struct intel_dp *intel_dp, intel_dp_compute_rate(intel_dp, crtc_state->port_clock, &link_bw, &rate_select); + /* + * WaEdpLinkRateDataReload + * + * Parade PS8461E MUX (used on varius TGL+ laptops) needs + * to snoop the link rates reported by the sink when we + * use LINK_RATE_SET in order to operate in jitter cleaning + * mode (as opposed to redriver mode). Unfortunately it + * loses track of the snooped link rates when powered down, + * so we need to make it re-snoop often. Without this high + * link rates are not stable. + */ + if (!link_bw) { + struct intel_connector *connector = intel_dp->attached_connector; + __le16 sink_rates[DP_MAX_SUPPORTED_RATES]; + + drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] Reloading eDP link rates\n", + connector->base.base.id, connector->base.name); + + drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES, + sink_rates, sizeof(sink_rates)); + } + if (link_bw) drm_dbg_kms(&i915->drm, "Using LINK_BW_SET value %02x\n", link_bw); -- 2.20.1