From f6aeda7d40707890f9ae4b72fdfea7f03b1c18e8 Mon Sep 17 00:00:00 2001 From: jsg Date: Thu, 31 Aug 2023 04:36:37 +0000 Subject: [PATCH] drm/i915/gt: Poll aux invalidation register bit on invalidation From Jonathan Cavitt 8e3f138b96f64fde58d74f886acbfd4baca907fc in linux-6.1.y/6.1.50 0fde2f23516a00fd90dfb980b66b4665fcbfa659 in mainline linux --- sys/dev/pci/drm/i915/gt/gen8_engine_cs.c | 17 ++++++++++++----- sys/dev/pci/drm/i915/gt/intel_gpu_commands.h | 1 + 2 files changed, 13 insertions(+), 5 deletions(-) diff --git a/sys/dev/pci/drm/i915/gt/gen8_engine_cs.c b/sys/dev/pci/drm/i915/gt/gen8_engine_cs.c index 6a8c2fab4ca..975e31d876b 100644 --- a/sys/dev/pci/drm/i915/gt/gen8_engine_cs.c +++ b/sys/dev/pci/drm/i915/gt/gen8_engine_cs.c @@ -184,7 +184,15 @@ u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32 *cs, const i915_reg_t inv *cs++ = MI_LOAD_REGISTER_IMM(1) | MI_LRI_MMIO_REMAP_EN; *cs++ = i915_mmio_reg_offset(inv_reg) + gsi_offset; *cs++ = AUX_INV; - *cs++ = MI_NOOP; + + *cs++ = MI_SEMAPHORE_WAIT_TOKEN | + MI_SEMAPHORE_REGISTER_POLL | + MI_SEMAPHORE_POLL | + MI_SEMAPHORE_SAD_EQ_SDD; + *cs++ = 0; + *cs++ = i915_mmio_reg_offset(inv_reg) + gsi_offset; + *cs++ = 0; + *cs++ = 0; return cs; } @@ -252,10 +260,9 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode) else if (engine->class == COMPUTE_CLASS) flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS; + count = 8; if (gen12_needs_ccs_aux_inv(rq->engine)) - count = 8 + 4; - else - count = 8; + count += 8; cs = intel_ring_begin(rq, count); if (IS_ERR(cs)) @@ -298,7 +305,7 @@ int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode) aux_inv = rq->engine->mask & ~GENMASK(_BCS(I915_MAX_BCS - 1), BCS0); if (aux_inv) - cmd += 4; + cmd += 8; } } diff --git a/sys/dev/pci/drm/i915/gt/intel_gpu_commands.h b/sys/dev/pci/drm/i915/gt/intel_gpu_commands.h index d4e9702d3c8..25ea5f8a464 100644 --- a/sys/dev/pci/drm/i915/gt/intel_gpu_commands.h +++ b/sys/dev/pci/drm/i915/gt/intel_gpu_commands.h @@ -120,6 +120,7 @@ #define MI_SEMAPHORE_TARGET(engine) ((engine)<<15) #define MI_SEMAPHORE_WAIT MI_INSTR(0x1c, 2) /* GEN8+ */ #define MI_SEMAPHORE_WAIT_TOKEN MI_INSTR(0x1c, 3) /* GEN12+ */ +#define MI_SEMAPHORE_REGISTER_POLL (1 << 16) #define MI_SEMAPHORE_POLL (1 << 15) #define MI_SEMAPHORE_SAD_GT_SDD (0 << 12) #define MI_SEMAPHORE_SAD_GTE_SDD (1 << 12) -- 2.20.1