From f51141b94601d6a67e546be87facbdc199ab5f51 Mon Sep 17 00:00:00 2001 From: jsg Date: Fri, 11 Jun 2021 05:33:16 +0000 Subject: [PATCH] limit workaround for AMD errata 400 to family 0fh and 10h AMD errata 400 "APIC Timer Interrupt Does Not Occur in Processor C-States" is only mentioned in the revision guides for family 0fh and 10h but we were checking for and disabling C1E on >= family 0fh. Since family 16h all the bits of the Interrupt Pending MSR the workaround uses are documented as read as zero. So this didn't cause any problems on real hardware but did on EPYC based AWS t3a instances according to Ilya Voronin who sent an initial patch to not attempt the workaround on family 17h. Tested on non-virtualised EPYC 7702P 17-31-00 by Hrvoje Popovski and Ryzen 5 2600X 17-08-02 by myself. ok mlarkin@ --- sys/arch/amd64/amd64/lapic.c | 5 ++--- sys/arch/i386/i386/lapic.c | 5 ++--- 2 files changed, 4 insertions(+), 6 deletions(-) diff --git a/sys/arch/amd64/amd64/lapic.c b/sys/arch/amd64/amd64/lapic.c index 6d82b6b2576..7232d629b51 100644 --- a/sys/arch/amd64/amd64/lapic.c +++ b/sys/arch/amd64/amd64/lapic.c @@ -1,4 +1,4 @@ -/* $OpenBSD: lapic.c,v 1.57 2020/09/06 20:50:00 cheloha Exp $ */ +/* $OpenBSD: lapic.c,v 1.58 2021/06/11 05:33:16 jsg Exp $ */ /* $NetBSD: lapic.c,v 1.2 2003/05/08 01:04:35 fvdl Exp $ */ /*- @@ -299,8 +299,7 @@ lapic_set_lvt(void) * Family 0Fh Processors" * #32559 revision 3.00 */ - if ((cpu_id & 0x00000f00) == 0x00000f00 && - (cpu_id & 0x0fff0000) >= 0x00040000) { + if (ci->ci_family == 0xf || ci->ci_family == 0x10) { uint64_t msr; msr = rdmsr(MSR_INT_PEN_MSG); diff --git a/sys/arch/i386/i386/lapic.c b/sys/arch/i386/i386/lapic.c index a67cf63263b..e995106202a 100644 --- a/sys/arch/i386/i386/lapic.c +++ b/sys/arch/i386/i386/lapic.c @@ -1,4 +1,4 @@ -/* $OpenBSD: lapic.c,v 1.47 2018/07/30 14:19:12 kettenis Exp $ */ +/* $OpenBSD: lapic.c,v 1.48 2021/06/11 05:33:16 jsg Exp $ */ /* $NetBSD: lapic.c,v 1.1.2.8 2000/02/23 06:10:50 sommerfeld Exp $ */ /*- @@ -160,8 +160,7 @@ lapic_set_lvt(void) * Family 0Fh Processors" * #32559 revision 3.00 */ - if ((cpu_id & 0x00000f00) == 0x00000f00 && - (cpu_id & 0x0fff0000) >= 0x00040000) { + if (ci->ci_family == 0xf || ci->ci_family == 0x10) { uint64_t msr; msr = rdmsr(MSR_INT_PEN_MSG); -- 2.20.1