From ea1c18cca58f9946ccffeea99c07ca8be35d4c28 Mon Sep 17 00:00:00 2001 From: jsg Date: Wed, 6 Mar 2024 00:05:49 +0000 Subject: [PATCH] regen --- sys/dev/pci/pcidevs.h | 92 +++++++++- sys/dev/pci/pcidevs_data.h | 362 ++++++++++++++++++++++++++++++++++++- 2 files changed, 452 insertions(+), 2 deletions(-) diff --git a/sys/dev/pci/pcidevs.h b/sys/dev/pci/pcidevs.h index ea87f34f714..d6c8f129edf 100644 --- a/sys/dev/pci/pcidevs.h +++ b/sys/dev/pci/pcidevs.h @@ -2,7 +2,7 @@ * THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT. * * generated from: - * OpenBSD: pcidevs,v 1.2066 2024/03/04 05:34:07 jsg Exp + * OpenBSD: pcidevs,v 1.2067 2024/03/06 00:05:18 jsg Exp */ /* $NetBSD: pcidevs,v 1.30 1997/06/24 06:20:24 thorpej Exp $ */ @@ -6379,7 +6379,97 @@ #define PCI_PRODUCT_INTEL_600SERIES_I2C_4 0x7afc /* 600 Series I2C */ #define PCI_PRODUCT_INTEL_600SERIES_I2C_5 0x7afd /* 600 Series I2C */ #define PCI_PRODUCT_INTEL_600SERIES_UART_2 0x7afe /* 600 Series UART */ +#define PCI_PRODUCT_INTEL_MTL_U4_HB 0x7d00 /* Core Ultra Host */ +#define PCI_PRODUCT_INTEL_MTL_H_HB_2 0x7d01 /* Core Ultra Host */ +#define PCI_PRODUCT_INTEL_MTL_U_HB_2 0x7d02 /* Core Ultra Host */ +#define PCI_PRODUCT_INTEL_MTL_DTT 0x7d03 /* Core Ultra DTT */ +#define PCI_PRODUCT_INTEL_MTL_VMD 0x7d0b /* Core Ultra VMD */ +#define PCI_PRODUCT_INTEL_MTL_PMT 0x7d0d /* Core Ultra PMT */ +#define PCI_PRODUCT_INTEL_MTL_H_HB_1 0x7d14 /* Core Ultra Host */ +#define PCI_PRODUCT_INTEL_MTL_U_HB_1 0x7d16 /* Core Ultra Host */ +#define PCI_PRODUCT_INTEL_MTL_IPU 0x7d19 /* Core Ultra IPU */ +#define PCI_PRODUCT_INTEL_MTL_NPU 0x7d1d /* Core Ultra NPU */ +#define PCI_PRODUCT_INTEL_MTL_U4_GT_1 0x7d40 /* Graphics */ +#define PCI_PRODUCT_INTEL_MTL_U_GT_1 0x7d45 /* Graphics */ +#define PCI_PRODUCT_INTEL_MTL_H_GT_1 0x7d55 /* Arc Graphics */ +#define PCI_PRODUCT_INTEL_MTL_U_GT_2 0x7d60 /* Graphics */ +#define PCI_PRODUCT_INTEL_MTL_H_GT_2 0x7dd5 /* Graphics */ +#define PCI_PRODUCT_INTEL_MTL_H_ESPI 0x7e02 /* Core Ultra eSPI */ +#define PCI_PRODUCT_INTEL_MTL_U_ESPI 0x7e03 /* Core Ultra eSPI */ +#define PCI_PRODUCT_INTEL_MTL_U4_ESPI 0x7e07 /* Core Ultra eSPI */ +#define PCI_PRODUCT_INTEL_MTL_P2SB_SOC 0x7e20 /* Core Ultra P2SB */ +#define PCI_PRODUCT_INTEL_MTL_PMC_SOC 0x7e21 /* Core Ultra PMC */ +#define PCI_PRODUCT_INTEL_MTL_SMB 0x7e22 /* Core Ultra SMBus */ +#define PCI_PRODUCT_INTEL_MTL_SPI 0x7e23 /* Core Ultra SPI */ +#define PCI_PRODUCT_INTEL_MTL_TH 0x7e24 /* Core Ultra TH */ +#define PCI_PRODUCT_INTEL_MTL_UART_0 0x7e25 /* Core Ultra UART */ +#define PCI_PRODUCT_INTEL_MTL_UART_1 0x7e26 /* Core Ultra UART */ +#define PCI_PRODUCT_INTEL_MTL_GSPI_0 0x7e27 /* Core Ultra GSPI */ +#define PCI_PRODUCT_INTEL_MTL_HDA 0x7e28 /* Core Ultra HD Audio */ +#define PCI_PRODUCT_INTEL_MTL_GSPI_1 0x7e30 /* Core Ultra GSPI */ +#define PCI_PRODUCT_INTEL_MTL_PCIE_1 0x7e38 /* Core Ultra PCIE */ +#define PCI_PRODUCT_INTEL_MTL_PCIE_2 0x7e39 /* Core Ultra PCIE */ +#define PCI_PRODUCT_INTEL_MTL_PCIE_3 0x7e3a /* Core Ultra PCIE */ +#define PCI_PRODUCT_INTEL_MTL_PCIE_4 0x7e3b /* Core Ultra PCIE */ +#define PCI_PRODUCT_INTEL_MTL_PCIE_5 0x7e3c /* Core Ultra PCIE */ +#define PCI_PRODUCT_INTEL_MTL_PCIE_6 0x7e3d /* Core Ultra PCIE */ +#define PCI_PRODUCT_INTEL_MTL_PCIE_7 0x7e3e /* Core Ultra PCIE */ +#define PCI_PRODUCT_INTEL_MTL_PCIE_8 0x7e3f /* Core Ultra PCIE */ #define PCI_PRODUCT_INTEL_WL_22500_14 0x7e40 /* Wi-Fi 6 AX210 */ +#define PCI_PRODUCT_INTEL_MTL_ISH 0x7e45 /* Core Ultra ISH */ +#define PCI_PRODUCT_INTEL_MTL_GSPI_2 0x7e46 /* Core Ultra GSPI */ +#define PCI_PRODUCT_INTEL_MTL_THC_0_1 0x7e48 /* Core Ultra THC */ +#define PCI_PRODUCT_INTEL_MTL_THC_0_2 0x7e49 /* Core Ultra THC */ +#define PCI_PRODUCT_INTEL_MTL_THC_1_1 0x7e4a /* Core Ultra THC */ +#define PCI_PRODUCT_INTEL_MTL_THC_1_2 0x7e4b /* Core Ultra THC */ +#define PCI_PRODUCT_INTEL_MTL_GNA 0x7e4c /* Core Ultra GNA */ +#define PCI_PRODUCT_INTEL_MTL_PCIE_9 0x7e4d /* Core Ultra PCIE */ +#define PCI_PRODUCT_INTEL_MTL_I2C_4 0x7e50 /* Core Ultra I2C */ +#define PCI_PRODUCT_INTEL_MTL_I2C_5 0x7e51 /* Core Ultra I2C */ +#define PCI_PRODUCT_INTEL_MTL_UART_2 0x7e52 /* Core Ultra UART */ +#define PCI_PRODUCT_INTEL_MTL_HECI_5 0x7e58 /* Core Ultra HECI */ +#define PCI_PRODUCT_INTEL_MTL_HECI_6 0x7e59 /* Core Ultra HECI */ +#define PCI_PRODUCT_INTEL_MTL_HECI_7 0x7e5a /* Core Ultra HECI */ +#define PCI_PRODUCT_INTEL_MTL_AHCI 0x7e63 /* Core Ultra AHCI */ +#define PCI_PRODUCT_INTEL_MTL_RAID_1 0x7e67 /* Core Ultra RAID */ +#define PCI_PRODUCT_INTEL_MTL_HECI_1 0x7e70 /* Core Ultra HECI */ +#define PCI_PRODUCT_INTEL_MTL_HECI_2 0x7e71 /* Core Ultra HECI */ +#define PCI_PRODUCT_INTEL_MTL_IDER 0x7e72 /* Core Ultra IDE-R */ +#define PCI_PRODUCT_INTEL_MTL_KT 0x7e73 /* Core Ultra KT */ +#define PCI_PRODUCT_INTEL_MTL_HECI_3 0x7e74 /* Core Ultra HECI */ +#define PCI_PRODUCT_INTEL_MTL_HECI_4 0x7e75 /* Core Ultra HECI */ +#define PCI_PRODUCT_INTEL_MTL_I2C_0 0x7e78 /* Core Ultra I2C */ +#define PCI_PRODUCT_INTEL_MTL_I2C_1 0x7e79 /* Core Ultra I2C */ +#define PCI_PRODUCT_INTEL_MTL_I2C_2 0x7e7a /* Core Ultra I2C */ +#define PCI_PRODUCT_INTEL_MTL_I2C_3 0x7e7b /* Core Ultra I2C */ +#define PCI_PRODUCT_INTEL_MTL_I3C 0x7e7c /* Core Ultra I3C */ +#define PCI_PRODUCT_INTEL_MTL_XHCI_2 0x7e7d /* Core Ultra xHCI */ +#define PCI_PRODUCT_INTEL_MTL_XDCI_2 0x7e7e /* Core Ultra xDCI */ +#define PCI_PRODUCT_INTEL_MTL_SRAM 0x7e7f /* Core Ultra SRAM */ +#define PCI_PRODUCT_INTEL_MTL_U4_XHCI 0x7eb0 /* Core Ultra xHCI */ +#define PCI_PRODUCT_INTEL_MTL_U4_XDCI 0x7eb1 /* Core Ultra xDCI */ +#define PCI_PRODUCT_INTEL_MTL_U4_TBT_DMA0 0x7eb2 /* Core Ultra TBT */ +#define PCI_PRODUCT_INTEL_MTL_U4_PCIE_16 0x7eb4 /* Core Ultra PCIE */ +#define PCI_PRODUCT_INTEL_MTL_U4_PCIE_17 0x7eb5 /* Core Ultra PCIE */ +#define PCI_PRODUCT_INTEL_MTL_U4_P2SB_IOE 0x7eb8 /* Core Ultra P2SB */ +#define PCI_PRODUCT_INTEL_MTL_U4_IEH_IOE 0x7eb9 /* Core Ultra IEH */ +#define PCI_PRODUCT_INTEL_MTL_U4_PMC_IOE 0x7ebe /* Core Ultra PMC */ +#define PCI_PRODUCT_INTEL_MTL_U4_SRAM_IOE 0x7ebf /* Core Ultra SRAM */ +#define PCI_PRODUCT_INTEL_MTL_XHCI_1 0x7ec0 /* Core Ultra xHCI */ +#define PCI_PRODUCT_INTEL_MTL_XDCI_1 0x7ec1 /* Core Ultra xDCI */ +#define PCI_PRODUCT_INTEL_MTL_TBT_DMA0 0x7ec2 /* Core Ultra TBT */ +#define PCI_PRODUCT_INTEL_MTL_TBT_DMA1 0x7ec3 /* Core Ultra TBT */ +#define PCI_PRODUCT_INTEL_MTL_PCIE_16 0x7ec4 /* Core Ultra PCIE */ +#define PCI_PRODUCT_INTEL_MTL_PCIE_17 0x7ec5 /* Core Ultra PCIE */ +#define PCI_PRODUCT_INTEL_MTL_PCIE_18 0x7ec6 /* Core Ultra PCIE */ +#define PCI_PRODUCT_INTEL_MTL_PCIE_19 0x7ec7 /* Core Ultra PCIE */ +#define PCI_PRODUCT_INTEL_MTL_P2SB_IOE 0x7ec8 /* Core Ultra P2SB */ +#define PCI_PRODUCT_INTEL_MTL_IEH_IOE 0x7ec9 /* Core Ultra IEH */ +#define PCI_PRODUCT_INTEL_MTL_PCIE_10 0x7eca /* Core Ultra PCIE */ +#define PCI_PRODUCT_INTEL_MTL_PCIE_11 0x7ecb /* Core Ultra PCIE */ +#define PCI_PRODUCT_INTEL_MTL_H_PCIE_12 0x7ecc /* Core Ultra PCIE */ +#define PCI_PRODUCT_INTEL_MTL_PMC_IOE 0x7ece /* Core Ultra PMC */ +#define PCI_PRODUCT_INTEL_MTL_SRAM_IOE 0x7ecf /* Core Ultra SRAM */ #define PCI_PRODUCT_INTEL_WL_22500_15 0x7f70 /* Wi-Fi 6 AX211 */ #define PCI_PRODUCT_INTEL_US15W_HB 0x8100 /* US15W Host */ #define PCI_PRODUCT_INTEL_US15L_HB 0x8101 /* US15L/UL11L Host */ diff --git a/sys/dev/pci/pcidevs_data.h b/sys/dev/pci/pcidevs_data.h index 529935fd45c..60991ad6d60 100644 --- a/sys/dev/pci/pcidevs_data.h +++ b/sys/dev/pci/pcidevs_data.h @@ -2,7 +2,7 @@ * THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT. * * generated from: - * OpenBSD: pcidevs,v 1.2066 2024/03/04 05:34:07 jsg Exp + * OpenBSD: pcidevs,v 1.2067 2024/03/06 00:05:18 jsg Exp */ /* $NetBSD: pcidevs,v 1.30 1997/06/24 06:20:24 thorpej Exp $ */ @@ -22855,10 +22855,370 @@ static const struct pci_known_product pci_known_products[] = { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_600SERIES_UART_2, "600 Series UART", }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_U4_HB, + "Core Ultra Host", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_H_HB_2, + "Core Ultra Host", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_U_HB_2, + "Core Ultra Host", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_DTT, + "Core Ultra DTT", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_VMD, + "Core Ultra VMD", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_PMT, + "Core Ultra PMT", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_H_HB_1, + "Core Ultra Host", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_U_HB_1, + "Core Ultra Host", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_IPU, + "Core Ultra IPU", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_NPU, + "Core Ultra NPU", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_U4_GT_1, + "Graphics", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_U_GT_1, + "Graphics", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_H_GT_1, + "Arc Graphics", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_U_GT_2, + "Graphics", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_H_GT_2, + "Graphics", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_H_ESPI, + "Core Ultra eSPI", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_U_ESPI, + "Core Ultra eSPI", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_U4_ESPI, + "Core Ultra eSPI", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_P2SB_SOC, + "Core Ultra P2SB", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_PMC_SOC, + "Core Ultra PMC", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_SMB, + "Core Ultra SMBus", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_SPI, + "Core Ultra SPI", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_TH, + "Core Ultra TH", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_UART_0, + "Core Ultra UART", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_UART_1, + "Core Ultra UART", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_GSPI_0, + "Core Ultra GSPI", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_HDA, + "Core Ultra HD Audio", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_GSPI_1, + "Core Ultra GSPI", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_PCIE_1, + "Core Ultra PCIE", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_PCIE_2, + "Core Ultra PCIE", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_PCIE_3, + "Core Ultra PCIE", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_PCIE_4, + "Core Ultra PCIE", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_PCIE_5, + "Core Ultra PCIE", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_PCIE_6, + "Core Ultra PCIE", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_PCIE_7, + "Core Ultra PCIE", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_PCIE_8, + "Core Ultra PCIE", + }, { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_22500_14, "Wi-Fi 6 AX210", }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_ISH, + "Core Ultra ISH", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_GSPI_2, + "Core Ultra GSPI", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_THC_0_1, + "Core Ultra THC", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_THC_0_2, + "Core Ultra THC", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_THC_1_1, + "Core Ultra THC", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_THC_1_2, + "Core Ultra THC", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_GNA, + "Core Ultra GNA", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_PCIE_9, + "Core Ultra PCIE", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_I2C_4, + "Core Ultra I2C", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_I2C_5, + "Core Ultra I2C", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_UART_2, + "Core Ultra UART", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_HECI_5, + "Core Ultra HECI", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_HECI_6, + "Core Ultra HECI", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_HECI_7, + "Core Ultra HECI", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_AHCI, + "Core Ultra AHCI", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_RAID_1, + "Core Ultra RAID", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_HECI_1, + "Core Ultra HECI", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_HECI_2, + "Core Ultra HECI", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_IDER, + "Core Ultra IDE-R", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_KT, + "Core Ultra KT", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_HECI_3, + "Core Ultra HECI", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_HECI_4, + "Core Ultra HECI", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_I2C_0, + "Core Ultra I2C", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_I2C_1, + "Core Ultra I2C", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_I2C_2, + "Core Ultra I2C", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_I2C_3, + "Core Ultra I2C", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_I3C, + "Core Ultra I3C", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_XHCI_2, + "Core Ultra xHCI", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_XDCI_2, + "Core Ultra xDCI", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_SRAM, + "Core Ultra SRAM", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_U4_XHCI, + "Core Ultra xHCI", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_U4_XDCI, + "Core Ultra xDCI", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_U4_TBT_DMA0, + "Core Ultra TBT", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_U4_PCIE_16, + "Core Ultra PCIE", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_U4_PCIE_17, + "Core Ultra PCIE", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_U4_P2SB_IOE, + "Core Ultra P2SB", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_U4_IEH_IOE, + "Core Ultra IEH", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_U4_PMC_IOE, + "Core Ultra PMC", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_U4_SRAM_IOE, + "Core Ultra SRAM", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_XHCI_1, + "Core Ultra xHCI", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_XDCI_1, + "Core Ultra xDCI", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_TBT_DMA0, + "Core Ultra TBT", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_TBT_DMA1, + "Core Ultra TBT", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_PCIE_16, + "Core Ultra PCIE", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_PCIE_17, + "Core Ultra PCIE", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_PCIE_18, + "Core Ultra PCIE", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_PCIE_19, + "Core Ultra PCIE", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_P2SB_IOE, + "Core Ultra P2SB", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_IEH_IOE, + "Core Ultra IEH", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_PCIE_10, + "Core Ultra PCIE", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_PCIE_11, + "Core Ultra PCIE", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_H_PCIE_12, + "Core Ultra PCIE", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_PMC_IOE, + "Core Ultra PMC", + }, + { + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_SRAM_IOE, + "Core Ultra SRAM", + }, { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_22500_15, "Wi-Fi 6 AX211", -- 2.20.1