From e333243a593e86a4ba805f7eb45032830d8a6885 Mon Sep 17 00:00:00 2001 From: jsg Date: Fri, 16 Sep 2022 02:24:23 +0000 Subject: [PATCH] drm/amdgpu: mmVM_L2_CNTL3 register not initialized correctly From Qu Huang ad5ef763dbbea8193bd2095a1401aeac6e8f74e8 in linux 5.15.y/5.15.68 b8983d42524f10ac6bf35bbce6a7cc8e45f61e04 in mainline linux --- sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c | 1 + 1 file changed, 1 insertion(+) diff --git a/sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c b/sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c index b3bede1dc41..4259f623a9d 100644 --- a/sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c +++ b/sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c @@ -176,6 +176,7 @@ static void mmhub_v1_0_init_cache_regs(struct amdgpu_device *adev) tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2, tmp); + tmp = mmVM_L2_CNTL3_DEFAULT; if (adev->gmc.translate_further) { tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12); tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, -- 2.20.1