From dd81489db8c6745c0e25d81d82e97f90d8886b12 Mon Sep 17 00:00:00 2001
From: jsg <jsg@openbsd.org>
Date: Mon, 29 Aug 2022 02:01:18 +0000
Subject: [PATCH] use ansi volatile keyword, not __volatile ok miod@ guenther@

---
 lib/libc/arch/aarch64/gen/fpgetround.c    |  4 ++--
 lib/libc/arch/aarch64/gen/fpgetsticky.c   |  4 ++--
 lib/libc/arch/aarch64/gen/fpsetround.c    |  6 +++---
 lib/libc/arch/aarch64/gen/fpsetsticky.c   |  6 +++---
 lib/libm/arch/aarch64/fenv.c              | 10 +++++-----
 sys/arch/amd64/include/atomic.h           |  4 ++--
 sys/arch/arm/arm/vfp.c                    | 10 +++++-----
 sys/arch/arm/include/atomic.h             |  4 ++--
 sys/arch/arm64/include/armreg.h           |  6 +++---
 sys/arch/arm64/include/atomic.h           |  4 ++--
 sys/arch/arm64/include/cpu.h              |  4 ++--
 sys/arch/i386/include/atomic.h            |  4 ++--
 sys/arch/m88k/include/atomic.h            |  4 ++--
 sys/arch/octeon/include/octeonvar.h       |  4 ++--
 sys/arch/powerpc/include/atomic.h         |  4 ++--
 sys/arch/powerpc64/include/atomic.h       |  4 ++--
 sys/arch/powerpc64/powerpc64/syncicache.c |  4 ++--
 sys/arch/riscv64/include/atomic.h         | 10 +++++-----
 sys/arch/riscv64/include/cpu.h            | 10 +++++-----
 sys/arch/riscv64/include/cpufunc.h        | 14 +++++++-------
 sys/arch/riscv64/include/riscvreg.h       | 20 ++++++++++----------
 sys/arch/riscv64/include/sbi.h            |  4 ++--
 sys/arch/riscv64/riscv64/pmap.c           |  4 ++--
 23 files changed, 74 insertions(+), 74 deletions(-)

diff --git a/lib/libc/arch/aarch64/gen/fpgetround.c b/lib/libc/arch/aarch64/gen/fpgetround.c
index 058fa8fcd8c..499f271434d 100644
--- a/lib/libc/arch/aarch64/gen/fpgetround.c
+++ b/lib/libc/arch/aarch64/gen/fpgetround.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: fpgetround.c,v 1.3 2021/12/13 18:28:39 deraadt Exp $	*/
+/*	$OpenBSD: fpgetround.c,v 1.4 2022/08/29 02:01:18 jsg Exp $	*/
 /*
  * Copyright (C) 2014 Andrew Turner
  * All rights reserved.
@@ -34,7 +34,7 @@ fpgetround(void)
 {
 	uint32_t fpscr;
 
-	__asm __volatile("mrs %x0, fpcr" : "=&r"(fpscr));
+	__asm volatile("mrs %x0, fpcr" : "=&r"(fpscr));
 
 	return ((fpscr >> 22) & 3);
 }
diff --git a/lib/libc/arch/aarch64/gen/fpgetsticky.c b/lib/libc/arch/aarch64/gen/fpgetsticky.c
index 723f6156479..0fec59d637a 100644
--- a/lib/libc/arch/aarch64/gen/fpgetsticky.c
+++ b/lib/libc/arch/aarch64/gen/fpgetsticky.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: fpgetsticky.c,v 1.2 2021/12/13 18:28:39 deraadt Exp $	*/
+/*	$OpenBSD: fpgetsticky.c,v 1.3 2022/08/29 02:01:18 jsg Exp $	*/
 /*
  * Copyright (C) 2014 Andrew Turner
  * All rights reserved.
@@ -40,7 +40,7 @@ fpgetsticky(void)
 {
 	fp_except old;
 
-	__asm __volatile("mrs %x0, fpcr" : "=&r"(old));
+	__asm volatile("mrs %x0, fpcr" : "=&r"(old));
 
 	return (old & FP_X_MASK);
 }
diff --git a/lib/libc/arch/aarch64/gen/fpsetround.c b/lib/libc/arch/aarch64/gen/fpsetround.c
index 0eba1541c6f..a3b39479f58 100644
--- a/lib/libc/arch/aarch64/gen/fpsetround.c
+++ b/lib/libc/arch/aarch64/gen/fpsetround.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: fpsetround.c,v 1.3 2021/12/13 18:28:39 deraadt Exp $	*/
+/*	$OpenBSD: fpsetround.c,v 1.4 2022/08/29 02:01:18 jsg Exp $	*/
 /*
  * Copyright (C) 2014 Andrew Turner
  * All rights reserved.
@@ -34,10 +34,10 @@ fpsetround(fp_rnd rnd_dir)
 {
 	uint32_t old, new;
 
-	__asm __volatile("mrs %x0, fpcr" : "=&r"(old));
+	__asm volatile("mrs %x0, fpcr" : "=&r"(old));
 	new = old & ~(3 << 22);
 	new |= rnd_dir << 22;
-	__asm __volatile("msr fpcr, %x0" : : "r"(new));
+	__asm volatile("msr fpcr, %x0" : : "r"(new));
 
 	return ((old >> 22) & 3);
 }
diff --git a/lib/libc/arch/aarch64/gen/fpsetsticky.c b/lib/libc/arch/aarch64/gen/fpsetsticky.c
index 592b777b739..e147d1f94c4 100644
--- a/lib/libc/arch/aarch64/gen/fpsetsticky.c
+++ b/lib/libc/arch/aarch64/gen/fpsetsticky.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: fpsetsticky.c,v 1.2 2021/12/13 18:28:39 deraadt Exp $	*/
+/*	$OpenBSD: fpsetsticky.c,v 1.3 2022/08/29 02:01:18 jsg Exp $	*/
 /*
  * Copyright (C) 2014 Andrew Turner
  * All rights reserved.
@@ -40,10 +40,10 @@ fpsetsticky(fp_except except)
 {
 	fp_except old, new;
 
-	__asm __volatile("mrs %x0, fpcr" : "=&r"(old));
+	__asm volatile("mrs %x0, fpcr" : "=&r"(old));
 	new = old & ~(FP_X_MASK);
 	new &= ~except;
-	__asm __volatile("msr fpcr, %x0" : : "r"(new));
+	__asm volatile("msr fpcr, %x0" : : "r"(new));
 
 	return (old & except);
 }
diff --git a/lib/libm/arch/aarch64/fenv.c b/lib/libm/arch/aarch64/fenv.c
index 7aca2b86b26..f660df6e342 100644
--- a/lib/libm/arch/aarch64/fenv.c
+++ b/lib/libm/arch/aarch64/fenv.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: fenv.c,v 1.4 2020/07/09 22:13:29 kettenis Exp $ */
+/* $OpenBSD: fenv.c,v 1.5 2022/08/29 02:01:18 jsg Exp $ */
 /*-
  * Copyright (c) 2004-2005 David Schultz <das@FreeBSD.ORG>
  * All rights reserved.
@@ -34,11 +34,11 @@
 #define	_FPUSW_SHIFT	8
 #define	_ENABLE_MASK	(FE_ALL_EXCEPT << _FPUSW_SHIFT)
 
-#define	__mrs_fpcr(r)	__asm __volatile("mrs %x0, fpcr" : "=r" (r))
-#define	__msr_fpcr(r)	__asm __volatile("msr fpcr, %x0" : : "r" (r))
+#define	__mrs_fpcr(r)	__asm volatile("mrs %x0, fpcr" : "=r" (r))
+#define	__msr_fpcr(r)	__asm volatile("msr fpcr, %x0" : : "r" (r))
 
-#define	__mrs_fpsr(r)	__asm __volatile("mrs %x0, fpsr" : "=r" (r))
-#define	__msr_fpsr(r)	__asm __volatile("msr fpsr, %x0" : : "r" (r))
+#define	__mrs_fpsr(r)	__asm volatile("mrs %x0, fpsr" : "=r" (r))
+#define	__msr_fpsr(r)	__asm volatile("msr fpsr, %x0" : : "r" (r))
 
 /*
  * The following constant represents the default floating-point environment
diff --git a/sys/arch/amd64/include/atomic.h b/sys/arch/amd64/include/atomic.h
index 6d737123e7b..58a85cf5921 100644
--- a/sys/arch/amd64/include/atomic.h
+++ b/sys/arch/amd64/include/atomic.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: atomic.h,v 1.21 2021/03/11 11:16:55 jsg Exp $	*/
+/*	$OpenBSD: atomic.h,v 1.22 2022/08/29 02:01:18 jsg Exp $	*/
 /*	$NetBSD: atomic.h,v 1.1 2003/04/26 18:39:37 fvdl Exp $	*/
 
 /*
@@ -260,7 +260,7 @@ _atomic_sub_long_nv(volatile unsigned long *p, unsigned long v)
  * ourselves.
  */
 
-#define __membar(_f) do { __asm __volatile(_f ::: "memory"); } while (0)
+#define __membar(_f) do { __asm volatile(_f ::: "memory"); } while (0)
 
 #if defined(MULTIPROCESSOR) || !defined(_KERNEL)
 #define membar_enter()		__membar("mfence")
diff --git a/sys/arch/arm/arm/vfp.c b/sys/arch/arm/arm/vfp.c
index 8f61fc8d395..1f37aecd55b 100644
--- a/sys/arch/arm/arm/vfp.c
+++ b/sys/arch/arm/arm/vfp.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: vfp.c,v 1.4 2019/03/13 09:28:21 patrick Exp $	*/
+/*	$OpenBSD: vfp.c,v 1.5 2022/08/29 02:01:18 jsg Exp $	*/
 
 /*
  * Copyright (c) 2011 Dale Rahn <drahn@openbsd.org>
@@ -28,7 +28,7 @@
 static inline void
 set_vfp_fpexc(uint32_t val)
 {
-	__asm __volatile(
+	__asm volatile(
 	    ".fpu vfpv3\n"
 	    "vmsr fpexc, %0" :: "r" (val));
 }
@@ -37,7 +37,7 @@ static inline uint32_t
 get_vfp_fpexc(void)
 {
 	uint32_t val;
-	__asm __volatile(
+	__asm volatile(
 	    ".fpu vfpv3\n"
 	    "vmrs %0, fpexc" : "=r" (val));
 	return val;
@@ -67,7 +67,7 @@ vfp_store(struct fpreg *vfpsave)
 	uint32_t scratch;
 
 	if (get_vfp_fpexc() & VFPEXC_EN) {
-		__asm __volatile(
+		__asm volatile(
 		    ".fpu vfpv3\n"
 		    "vstmia	%1!, {d0-d15}\n"	/* d0-d15 */
 		    "vstmia	%1!, {d16-d31}\n"	/* d16-d31 */
@@ -151,7 +151,7 @@ vfp_load(struct proc *p)
 	/* enable to be able to load ctx */
 	set_vfp_fpexc(VFPEXC_EN);
 
-	__asm __volatile(
+	__asm volatile(
 	    ".fpu vfpv3\n"
 	    "vldmia	%1!, {d0-d15}\n"		/* d0-d15 */
 	    "vldmia	%1!, {d16-d31}\n"		/* d16-d31 */
diff --git a/sys/arch/arm/include/atomic.h b/sys/arch/arm/include/atomic.h
index 33b43833dfa..02c33790c68 100644
--- a/sys/arch/arm/include/atomic.h
+++ b/sys/arch/arm/include/atomic.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: atomic.h,v 1.18 2017/07/31 11:52:49 kettenis Exp $	*/
+/*	$OpenBSD: atomic.h,v 1.19 2022/08/29 02:01:18 jsg Exp $	*/
 
 /* Public Domain */
 
@@ -234,7 +234,7 @@ _def_atomic_sub_nv(_atomic_sub_long_nv, unsigned long)
 #define atomic_sub_int_nv(_p, _v) _atomic_sub_int_nv((_p), (_v))
 #define atomic_sub_long_nv(_p, _v) _atomic_sub_long_nv((_p), (_v))
 
-#define __membar(_f) do { __asm __volatile(_f ::: "memory"); } while (0)
+#define __membar(_f) do { __asm volatile(_f ::: "memory"); } while (0)
 
 #define membar_enter()		__membar("dmb sy")
 #define membar_exit()		__membar("dmb sy")
diff --git a/sys/arch/arm64/include/armreg.h b/sys/arch/arm64/include/armreg.h
index 851f06f8266..0c181801e0c 100644
--- a/sys/arch/arm64/include/armreg.h
+++ b/sys/arch/arm64/include/armreg.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: armreg.h,v 1.20 2022/08/24 22:01:16 kettenis Exp $ */
+/* $OpenBSD: armreg.h,v 1.21 2022/08/29 02:01:18 jsg Exp $ */
 /*-
  * Copyright (c) 2013, 2014 Andrew Turner
  * Copyright (c) 2015 The FreeBSD Foundation
@@ -38,11 +38,11 @@
 
 #define	READ_SPECIALREG(reg)						\
 ({	uint64_t val;							\
-	__asm __volatile("mrs	%0, " __STRING(reg) : "=&r" (val));	\
+	__asm volatile("mrs	%0, " __STRING(reg) : "=&r" (val));	\
 	val;								\
 })
 #define	WRITE_SPECIALREG(reg, val)					\
-	__asm __volatile("msr	" __STRING(reg) ", %0" : : "r"((uint64_t)val))
+	__asm volatile("msr	" __STRING(reg) ", %0" : : "r"((uint64_t)val))
 
 /* CCSIDR_EL1 - Current Cache Size ID Register */
 #define	CCSIDR_SETS_MASK	0x0fffe000
diff --git a/sys/arch/arm64/include/atomic.h b/sys/arch/arm64/include/atomic.h
index 5cf42178cb5..5337e3a2d24 100644
--- a/sys/arch/arm64/include/atomic.h
+++ b/sys/arch/arm64/include/atomic.h
@@ -1,11 +1,11 @@
-/* $OpenBSD: atomic.h,v 1.3 2017/05/12 08:48:31 mpi Exp $ */
+/* $OpenBSD: atomic.h,v 1.4 2022/08/29 02:01:18 jsg Exp $ */
 
 /* Public Domain */
 
 #ifndef _MACHINE_ATOMIC_H_
 #define _MACHINE_ATOMIC_H_
 
-#define __membar(_f) do { __asm __volatile(_f ::: "memory"); } while (0)
+#define __membar(_f) do { __asm volatile(_f ::: "memory"); } while (0)
 
 #define membar_enter()		__membar("dmb sy")
 #define membar_exit()		__membar("dmb sy")
diff --git a/sys/arch/arm64/include/cpu.h b/sys/arch/arm64/include/cpu.h
index 1f3bebe56b4..b096597a3f6 100644
--- a/sys/arch/arm64/include/cpu.h
+++ b/sys/arch/arm64/include/cpu.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: cpu.h,v 1.27 2022/07/13 09:28:19 kettenis Exp $ */
+/* $OpenBSD: cpu.h,v 1.28 2022/08/29 02:01:18 jsg Exp $ */
 /*
  * Copyright (c) 2016 Dale Rahn <drahn@dalerahn.com>
  *
@@ -158,7 +158,7 @@ static inline struct cpu_info *
 curcpu(void)
 {
 	struct cpu_info *__ci = NULL;
-	__asm __volatile("mrs %0, tpidr_el1" : "=r" (__ci));
+	__asm volatile("mrs %0, tpidr_el1" : "=r" (__ci));
 	return (__ci);
 }
 
diff --git a/sys/arch/i386/include/atomic.h b/sys/arch/i386/include/atomic.h
index 4cc1f2b49da..45aedb819c8 100644
--- a/sys/arch/i386/include/atomic.h
+++ b/sys/arch/i386/include/atomic.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: atomic.h,v 1.19 2021/03/11 11:16:57 jsg Exp $	*/
+/*	$OpenBSD: atomic.h,v 1.20 2022/08/29 02:01:18 jsg Exp $	*/
 /* $NetBSD: atomic.h,v 1.1.2.2 2000/02/21 18:54:07 sommerfeld Exp $ */
 
 /*-
@@ -244,7 +244,7 @@ _atomic_sub_long_nv(volatile unsigned long *p, unsigned long v)
  * ourselves.
  */
 
-#define __membar(_f) do { __asm __volatile(_f ::: "memory"); } while (0)
+#define __membar(_f) do { __asm volatile(_f ::: "memory"); } while (0)
 
 #if defined(MULTIPROCESSOR) || !defined(_KERNEL)
 #define membar_enter()		__membar("lock; addl $0,0(%%esp)")
diff --git a/sys/arch/m88k/include/atomic.h b/sys/arch/m88k/include/atomic.h
index b4f078d2444..06862aa1f0e 100644
--- a/sys/arch/m88k/include/atomic.h
+++ b/sys/arch/m88k/include/atomic.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: atomic.h,v 1.15 2021/05/04 14:05:12 aoyama Exp $	*/
+/*	$OpenBSD: atomic.h,v 1.16 2022/08/29 02:01:18 jsg Exp $	*/
 
 /* Public Domain */
 
@@ -187,7 +187,7 @@ __sync_synchronize(void)
 
 /* trap numbers below 128 would cause a privileged instruction fault */
 #define	__membar() do {						\
-	__asm __volatile("tb1 0, %%r0, 128" ::: "memory");	\
+	__asm volatile("tb1 0, %%r0, 128" ::: "memory");	\
 } while (0)
 
 #endif	/* gcc < 4 */
diff --git a/sys/arch/octeon/include/octeonvar.h b/sys/arch/octeon/include/octeonvar.h
index 2ba34e615f0..38b6f05fa41 100644
--- a/sys/arch/octeon/include/octeonvar.h
+++ b/sys/arch/octeon/include/octeonvar.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: octeonvar.h,v 1.53 2021/03/11 11:16:59 jsg Exp $	*/
+/*	$OpenBSD: octeonvar.h,v 1.54 2022/08/29 02:01:18 jsg Exp $	*/
 /*	$NetBSD: maltavar.h,v 1.3 2002/03/18 10:10:16 simonb Exp $	*/
 
 /*-
@@ -353,7 +353,7 @@ ffs32(uint32_t val)
 {
 	int ret;
 
-	__asm __volatile ( \
+	__asm volatile ( \
 		_ASM_PROLOGUE_MIPS64
 		"	clz	%0, %1			\n"
 		_ASM_EPILOGUE
diff --git a/sys/arch/powerpc/include/atomic.h b/sys/arch/powerpc/include/atomic.h
index f543a284d85..56586da8397 100644
--- a/sys/arch/powerpc/include/atomic.h
+++ b/sys/arch/powerpc/include/atomic.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: atomic.h,v 1.12 2019/07/11 21:18:05 kettenis Exp $	*/
+/*	$OpenBSD: atomic.h,v 1.13 2022/08/29 02:01:18 jsg Exp $	*/
 
 /*
  * Copyright (c) 2015 Martin Pieuchot
@@ -273,7 +273,7 @@ _atomic_addic_long_nv(volatile unsigned long *p, unsigned long v)
 #define atomic_inc_long_nv(_p) _atomic_addic_long_nv((_p), 1)
 #define atomic_dec_long_nv(_p) _atomic_addic_long_nv((_p), -1)
 
-#define __membar(_f) do { __asm __volatile(_f ::: "memory"); } while (0)
+#define __membar(_f) do { __asm volatile(_f ::: "memory"); } while (0)
 
 #if defined(MULTIPROCESSOR) || !defined(_KERNEL)
 #define membar_enter()		__membar("isync")
diff --git a/sys/arch/powerpc64/include/atomic.h b/sys/arch/powerpc64/include/atomic.h
index 2f58aa80db7..cd234e81a8f 100644
--- a/sys/arch/powerpc64/include/atomic.h
+++ b/sys/arch/powerpc64/include/atomic.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: atomic.h,v 1.2 2020/07/01 18:25:31 kettenis Exp $	*/
+/*	$OpenBSD: atomic.h,v 1.3 2022/08/29 02:01:18 jsg Exp $	*/
 
 /*
  * Copyright (c) 2015 Martin Pieuchot
@@ -273,7 +273,7 @@ _atomic_addic_long_nv(volatile unsigned long *p, unsigned long v)
 #define atomic_inc_long_nv(_p) _atomic_addic_long_nv((_p), 1)
 #define atomic_dec_long_nv(_p) _atomic_addic_long_nv((_p), -1)
 
-#define __membar(_f) do { __asm __volatile(_f ::: "memory"); } while (0)
+#define __membar(_f) do { __asm volatile(_f ::: "memory"); } while (0)
 
 #if defined(MULTIPROCESSOR) || !defined(_KERNEL)
 #define membar_enter()		__membar("isync")
diff --git a/sys/arch/powerpc64/powerpc64/syncicache.c b/sys/arch/powerpc64/powerpc64/syncicache.c
index 292d10a662a..d462efbfbf7 100644
--- a/sys/arch/powerpc64/powerpc64/syncicache.c
+++ b/sys/arch/powerpc64/powerpc64/syncicache.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: syncicache.c,v 1.3 2020/06/26 20:58:38 kettenis Exp $	*/
+/*	$OpenBSD: syncicache.c,v 1.4 2022/08/29 02:01:18 jsg Exp $	*/
 
 /*-
  * SPDX-License-Identifier: BSD-4-Clause
@@ -58,7 +58,7 @@ __syncicache(void *from, size_t len)
 	__asm volatile ("sync");
 	p = (char *)from - off;
 	do {
-		__asm __volatile ("icbi 0,%0" :: "r"(p));
+		__asm volatile ("icbi 0,%0" :: "r"(p));
 		p += cacheline_size;
 		len -= cacheline_size;
 	} while (len + cacheline_size > cacheline_size);
diff --git a/sys/arch/riscv64/include/atomic.h b/sys/arch/riscv64/include/atomic.h
index 24b5f532be2..fca8aac9552 100644
--- a/sys/arch/riscv64/include/atomic.h
+++ b/sys/arch/riscv64/include/atomic.h
@@ -1,11 +1,11 @@
-/*	$OpenBSD: atomic.h,v 1.3 2021/06/25 13:25:53 jsg Exp $	*/
+/*	$OpenBSD: atomic.h,v 1.4 2022/08/29 02:01:18 jsg Exp $	*/
 
 /* Public Domain */
 
 #ifndef _MACHINE_ATOMIC_H_
 #define _MACHINE_ATOMIC_H_
 
-#define __membar(_f) do {__asm __volatile(_f ::: "memory"); } while (0)
+#define __membar(_f) do {__asm volatile(_f ::: "memory"); } while (0)
 
 #define membar_enter()		__membar("fence w,rw")
 #define membar_exit()		__membar("fence rw,w")
@@ -27,7 +27,7 @@
 static inline void
 atomic_setbits_int(volatile unsigned int *p, unsigned int v)
 {
-	__asm __volatile("amoor.w zero, %1, %0"
+	__asm volatile("amoor.w zero, %1, %0"
 			: "+A" (*p)
 			: "r" (v)
 			: "memory");
@@ -36,7 +36,7 @@ atomic_setbits_int(volatile unsigned int *p, unsigned int v)
 static inline void
 atomic_store_64(volatile uint64_t *p, uint64_t v)
 {
-	__asm __volatile("amoor.d zero, %1, %0"
+	__asm volatile("amoor.d zero, %1, %0"
 			: "+A" (*p)
 			: "r" (v)
 			: "memory");
@@ -49,7 +49,7 @@ atomic_store_64(volatile uint64_t *p, uint64_t v)
 static inline void
 atomic_clearbits_int(volatile unsigned int *p, unsigned int v)
 {
-	__asm __volatile("amoand.w zero, %1, %0"
+	__asm volatile("amoand.w zero, %1, %0"
 			: "+A" (*p)
 			: "r" (~v)
 			: "memory");
diff --git a/sys/arch/riscv64/include/cpu.h b/sys/arch/riscv64/include/cpu.h
index a455820bb7c..b90219e6050 100644
--- a/sys/arch/riscv64/include/cpu.h
+++ b/sys/arch/riscv64/include/cpu.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cpu.h,v 1.13 2022/08/09 04:49:08 cheloha Exp $	*/
+/*	$OpenBSD: cpu.h,v 1.14 2022/08/29 02:01:18 jsg Exp $	*/
 
 /*
  * Copyright (c) 2019 Mike Larkin <mlarkin@openbsd.org>
@@ -137,7 +137,7 @@ static inline struct cpu_info *
 curcpu(void)
 {
 	struct cpu_info *__ci = NULL;
-	__asm __volatile("mv %0, tp" : "=&r"(__ci));
+	__asm volatile("mv %0, tp" : "=&r"(__ci));
 	return (__ci);
 }
 
@@ -238,7 +238,7 @@ void	savectx		(struct pcb *pcb);
 static inline void
 intr_enable(void)
 {
-	__asm __volatile("csrsi sstatus, %0" :: "i" (SSTATUS_SIE));
+	__asm volatile("csrsi sstatus, %0" :: "i" (SSTATUS_SIE));
 }
 
 static inline u_long
@@ -246,7 +246,7 @@ intr_disable(void)
 {
 	uint64_t ret;
 
-	__asm __volatile(
+	__asm volatile(
 	    "csrrci %0, sstatus, %1"
 	    : "=&r" (ret) : "i" (SSTATUS_SIE)
 	);
@@ -257,7 +257,7 @@ intr_disable(void)
 static inline void
 intr_restore(u_long s)
 {
-	__asm __volatile("csrs sstatus, %0" :: "r" (s));
+	__asm volatile("csrs sstatus, %0" :: "r" (s));
 }
 
 void	delay (unsigned);
diff --git a/sys/arch/riscv64/include/cpufunc.h b/sys/arch/riscv64/include/cpufunc.h
index 884a1ed642a..13ddca74501 100644
--- a/sys/arch/riscv64/include/cpufunc.h
+++ b/sys/arch/riscv64/include/cpufunc.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cpufunc.h,v 1.4 2021/05/18 09:14:49 kettenis Exp $	*/
+/*	$OpenBSD: cpufunc.h,v 1.5 2022/08/29 02:01:18 jsg Exp $	*/
 
 /*-
  * Copyright (c) 2014 Andrew Turner
@@ -49,19 +49,19 @@ breakpoint(void)
 static __inline void
 fence_i(void)
 {
-	__asm __volatile("fence.i" ::: "memory");
+	__asm volatile("fence.i" ::: "memory");
 }
 
 static __inline void
 sfence_vma(void)
 {
-	__asm __volatile("sfence.vma" ::: "memory");
+	__asm volatile("sfence.vma" ::: "memory");
 }
 
 static __inline void
 sfence_vma_page(uintptr_t addr)
 {
-	__asm __volatile("sfence.vma %0"
+	__asm volatile("sfence.vma %0"
 			:
 			: "r" (addr)
 			: "memory");
@@ -71,7 +71,7 @@ sfence_vma_page(uintptr_t addr)
 static __inline void
 sfence_vma_asid(uint64_t asid)
 {
-	__asm __volatile("sfence.vma x0, %0"
+	__asm volatile("sfence.vma x0, %0"
 			:
 			: "r" (asid)
 			: "memory");
@@ -80,7 +80,7 @@ sfence_vma_asid(uint64_t asid)
 static __inline void
 sfence_vma_page_asid(uintptr_t addr, uint64_t asid)
 {
-	__asm __volatile("sfence.vma %0, %1"
+	__asm volatile("sfence.vma %0, %1"
 			 :
 			 : "r" (addr), "r" (asid)
 			 : "memory");
@@ -96,7 +96,7 @@ extern void (*cpu_dcache_wb_range)(paddr_t, psize_t);
 static __inline void
 load_satp(uint64_t val)
 {
-	__asm __volatile("csrw satp, %0" :: "r"(val));
+	__asm volatile("csrw satp, %0" :: "r"(val));
 }
 
 #define	cpufunc_nullop()		riscv_nullop()
diff --git a/sys/arch/riscv64/include/riscvreg.h b/sys/arch/riscv64/include/riscvreg.h
index e57720d499c..823ad3aaf1c 100644
--- a/sys/arch/riscv64/include/riscvreg.h
+++ b/sys/arch/riscv64/include/riscvreg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: riscvreg.h,v 1.4 2021/07/06 19:09:57 patrick Exp $	*/
+/*	$OpenBSD: riscvreg.h,v 1.5 2022/08/29 02:01:18 jsg Exp $	*/
 
 /*-
  * Copyright (c) 2019 Brian Bamsch <bbamsch@google.com>
@@ -197,38 +197,38 @@
 
 #define csr_swap(csr, val)						\
 ({	if (CSR_ZIMM(val))						\
-		__asm __volatile("csrrwi %0, " #csr ", %1"		\
+		__asm volatile("csrrwi %0, " #csr ", %1"		\
 				: "=r" (val) : "i" (val));		\
 	else								\
-		__asm __volatile("csrrw %0, " #csr ", %1"		\
+		__asm volatile("csrrw %0, " #csr ", %1"		\
 				: "=r" (val) : "r" (val));		\
 	val;								\
 })
 
 #define csr_write(csr, val)						\
 ({	if (CSR_ZIMM(val))						\
-		__asm __volatile("csrwi " #csr ", %0" :: "i" (val));	\
+		__asm volatile("csrwi " #csr ", %0" :: "i" (val));	\
 	else								\
-		__asm __volatile("csrw " #csr ", %0" ::  "r" (val));	\
+		__asm volatile("csrw " #csr ", %0" ::  "r" (val));	\
 })
 
 #define csr_set(csr, val)						\
 ({	if (CSR_ZIMM(val))						\
-		__asm __volatile("csrsi " #csr ", %0" :: "i" (val));	\
+		__asm volatile("csrsi " #csr ", %0" :: "i" (val));	\
 	else								\
-		__asm __volatile("csrs " #csr ", %0" :: "r" (val));	\
+		__asm volatile("csrs " #csr ", %0" :: "r" (val));	\
 })
 
 #define csr_clear(csr, val)						\
 ({	if (CSR_ZIMM(val))						\
-		__asm __volatile("csrci " #csr ", %0" :: "i" (val));	\
+		__asm volatile("csrci " #csr ", %0" :: "i" (val));	\
 	else								\
-		__asm __volatile("csrc " #csr ", %0" :: "r" (val));	\
+		__asm volatile("csrc " #csr ", %0" :: "r" (val));	\
 })
 
 #define csr_read(csr)							\
 ({	u_long val;							\
-	__asm __volatile("csrr %0, " #csr : "=r" (val));		\
+	__asm volatile("csrr %0, " #csr : "=r" (val));		\
 	val;								\
 })
 
diff --git a/sys/arch/riscv64/include/sbi.h b/sys/arch/riscv64/include/sbi.h
index 0cb68d797f8..802ae7f68a0 100644
--- a/sys/arch/riscv64/include/sbi.h
+++ b/sys/arch/riscv64/include/sbi.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: sbi.h,v 1.4 2021/07/02 08:44:37 kettenis Exp $	*/
+/*	$OpenBSD: sbi.h,v 1.5 2022/08/29 02:01:18 jsg Exp $	*/
 
 /*-
  * Copyright (c) 2016-2017 Ruslan Bukin <br@bsdpad.com>
@@ -116,7 +116,7 @@ sbi_call(uint64_t arg7, uint64_t arg6, uint64_t arg0, uint64_t arg1,
 	register uintptr_t a6 __asm ("a6") = (uintptr_t)(arg6);
 	register uintptr_t a7 __asm ("a7") = (uintptr_t)(arg7);
 
-	__asm __volatile(			\
+	__asm volatile(			\
 		"ecall"				\
 		:"+r"(a0), "+r"(a1)		\
 		:"r"(a2), "r"(a3), "r"(a6), "r"(a7)	\
diff --git a/sys/arch/riscv64/riscv64/pmap.c b/sys/arch/riscv64/riscv64/pmap.c
index 87bcca8c7e8..a1dcc203222 100644
--- a/sys/arch/riscv64/riscv64/pmap.c
+++ b/sys/arch/riscv64/riscv64/pmap.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: pmap.c,v 1.21 2022/01/01 11:45:35 kettenis Exp $	*/
+/*	$OpenBSD: pmap.c,v 1.22 2022/08/29 02:01:18 jsg Exp $	*/
 
 /*
  * Copyright (c) 2019-2020 Brian Bamsch <bbamsch@google.com>
@@ -1328,7 +1328,7 @@ pmap_bootstrap(long kvo, vaddr_t l1pt, vaddr_t kernelstart, vaddr_t kernelend,
 
 	//switching to new page table
 	uint64_t satp = pmap_kernel()->pm_satp;
-	__asm __volatile("csrw satp, %0" :: "r" (satp) : "memory");
+	__asm volatile("csrw satp, %0" :: "r" (satp) : "memory");
 
 	printf("all mapped\n");
 
-- 
2.20.1