From d7e3b16576e2c4fddf7397ab0bd59ce9ec0f39ff Mon Sep 17 00:00:00 2001 From: jsg Date: Mon, 9 Jan 2023 04:07:06 +0000 Subject: [PATCH] drm/amdgpu: fix mmhub register base coding error From Yang Wang 51c107f91bf1d49fdd1538e46770e6f146f40267 in linux-6.1.y/6.1.4 347fafe0eb46df941965c355c77ce480e4d49f1f in mainline linux --- sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c | 2 +- sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c | 2 +- sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c | 2 +- sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c | 2 +- sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c b/sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c index 998b5d17b27..0e664d0cc8d 100644 --- a/sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c +++ b/sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c @@ -319,7 +319,7 @@ static void mmhub_v2_0_init_cache_regs(struct amdgpu_device *adev) tmp = mmMMVM_L2_CNTL5_DEFAULT; tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0); - WREG32_SOC15(GC, 0, mmMMVM_L2_CNTL5, tmp); + WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL5, tmp); } static void mmhub_v2_0_enable_system_domain(struct amdgpu_device *adev) diff --git a/sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c b/sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c index 1b027d069ab..4638ea7c2ee 100644 --- a/sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c +++ b/sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c @@ -243,7 +243,7 @@ static void mmhub_v2_3_init_cache_regs(struct amdgpu_device *adev) tmp = mmMMVM_L2_CNTL5_DEFAULT; tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0); - WREG32_SOC15(GC, 0, mmMMVM_L2_CNTL5, tmp); + WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL5, tmp); } static void mmhub_v2_3_enable_system_domain(struct amdgpu_device *adev) diff --git a/sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c b/sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c index a1d26c4d80b..16cc82215e2 100644 --- a/sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c +++ b/sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c @@ -275,7 +275,7 @@ static void mmhub_v3_0_init_cache_regs(struct amdgpu_device *adev) tmp = regMMVM_L2_CNTL5_DEFAULT; tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0); - WREG32_SOC15(GC, 0, regMMVM_L2_CNTL5, tmp); + WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL5, tmp); } static void mmhub_v3_0_enable_system_domain(struct amdgpu_device *adev) diff --git a/sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c b/sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c index e8058edc1d1..6bdf2ef0298 100644 --- a/sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c +++ b/sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c @@ -269,7 +269,7 @@ static void mmhub_v3_0_1_init_cache_regs(struct amdgpu_device *adev) tmp = regMMVM_L2_CNTL5_DEFAULT; tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0); - WREG32_SOC15(GC, 0, regMMVM_L2_CNTL5, tmp); + WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL5, tmp); } static void mmhub_v3_0_1_enable_system_domain(struct amdgpu_device *adev) diff --git a/sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c b/sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c index 770be0a8f7c..45465acaa94 100644 --- a/sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c +++ b/sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c @@ -268,7 +268,7 @@ static void mmhub_v3_0_2_init_cache_regs(struct amdgpu_device *adev) tmp = regMMVM_L2_CNTL5_DEFAULT; tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0); - WREG32_SOC15(GC, 0, regMMVM_L2_CNTL5, tmp); + WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL5, tmp); } static void mmhub_v3_0_2_enable_system_domain(struct amdgpu_device *adev) -- 2.20.1