From d732de986b8a3e1aa5a3186dbe2b8d902d73cda0 Mon Sep 17 00:00:00 2001 From: jsg Date: Fri, 2 Feb 2024 03:39:56 +0000 Subject: [PATCH] drm/amdgpu/gfx10: set UNORD_DISPATCH in compute MQDs From Alex Deucher b59ea95e72e051fe53a5c978222d65b80ca2ef96 in linux-6.6.y/6.6.15 03ff6d7238b77e5fb2b85dc5fe01d2db9eb893bd in mainline linux --- sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c | 2 +- sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v10.c | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c b/sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c index 965c86cc311..8e9e703199b 100644 --- a/sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c +++ b/sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c @@ -6572,7 +6572,7 @@ static int gfx_v10_0_compute_mqd_init(struct amdgpu_device *adev, void *m, #ifdef __BIG_ENDIAN tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); #endif - tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); diff --git a/sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v10.c b/sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v10.c index 8b7fed91352..22cbfa1bdad 100644 --- a/sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v10.c +++ b/sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v10.c @@ -170,6 +170,7 @@ static void update_mqd(struct mqd_manager *mm, void *mqd, m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; m->cp_hqd_pq_control |= ffs(q->queue_size / sizeof(unsigned int)) - 1 - 1; + m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK; pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); -- 2.20.1