From d02a7d534e008bfe0347db4a5d921a65cade0160 Mon Sep 17 00:00:00 2001 From: jsg Date: Wed, 5 May 2021 01:28:38 +0000 Subject: [PATCH] riscv: Assert that SUM is not set in SSTATUS for exceptions. From John Baldwin 6a3a6fe34bf36b6e745b3e9ad1a991de057729c7 in FreeBSD ok kettenis@ mlarkin@ --- sys/arch/riscv64/riscv64/trap.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/sys/arch/riscv64/riscv64/trap.c b/sys/arch/riscv64/riscv64/trap.c index fd84ee9a6ae..7e1286ee013 100644 --- a/sys/arch/riscv64/riscv64/trap.c +++ b/sys/arch/riscv64/riscv64/trap.c @@ -67,6 +67,9 @@ do_trap_supervisor(struct trapframe *frame) KASSERTMSG((csr_read(sstatus) & (SSTATUS_SPP | SSTATUS_SIE)) == SSTATUS_SPP, "Came from S mode with interrupts enabled"); + KASSERTMSG((csr_read(sstatus) & (SSTATUS_SUM)) == 0, + "Came from S mode with SUM enabled"); + if (frame->tf_scause & EXCP_INTR) { /* Interrupt */ riscv_cpu_intr(frame); @@ -119,6 +122,9 @@ do_trap_user(struct trapframe *frame) KASSERTMSG((csr_read(sstatus) & (SSTATUS_SPP | SSTATUS_SIE)) == 0, "Came from U mode with interrupts enabled"); + KASSERTMSG((csr_read(sstatus) & (SSTATUS_SUM)) == 0, + "Came from U mode with SUM enabled"); + /* Save fpu context before (possibly) calling interrupt handler. * Could end up context switching in interrupt handler. */ -- 2.20.1