From ce2260ec3e786fce456edf4e398ec8b5dfd83e84 Mon Sep 17 00:00:00 2001 From: miod Date: Mon, 21 Aug 2023 20:17:30 +0000 Subject: [PATCH] Remove dead code. --- sys/arch/riscv64/conf/files.riscv64 | 3 +- sys/arch/riscv64/include/cpufunc.h | 6 +--- sys/arch/riscv64/riscv64/cpufunc_asm.S | 43 -------------------------- 3 files changed, 2 insertions(+), 50 deletions(-) delete mode 100644 sys/arch/riscv64/riscv64/cpufunc_asm.S diff --git a/sys/arch/riscv64/conf/files.riscv64 b/sys/arch/riscv64/conf/files.riscv64 index 5ddd3d2024f..d69543ee356 100644 --- a/sys/arch/riscv64/conf/files.riscv64 +++ b/sys/arch/riscv64/conf/files.riscv64 @@ -1,4 +1,4 @@ -# $OpenBSD: files.riscv64,v 1.25 2023/07/08 10:06:13 kettenis Exp $ +# $OpenBSD: files.riscv64,v 1.26 2023/08/21 20:17:30 miod Exp $ # Standard stanzas config(8) can't run without maxpartitions 16 @@ -35,7 +35,6 @@ file arch/riscv64/riscv64/syscall.c file arch/riscv64/riscv64/pagezero.S file arch/riscv64/riscv64/trap.c file arch/riscv64/riscv64/sbi.c -file arch/riscv64/riscv64/cpufunc_asm.S file arch/riscv64/riscv64/fpu.c file arch/riscv64/riscv64/db_disasm.c ddb diff --git a/sys/arch/riscv64/include/cpufunc.h b/sys/arch/riscv64/include/cpufunc.h index 13ddca74501..a55a06fcd3a 100644 --- a/sys/arch/riscv64/include/cpufunc.h +++ b/sys/arch/riscv64/include/cpufunc.h @@ -1,4 +1,4 @@ -/* $OpenBSD: cpufunc.h,v 1.5 2022/08/29 02:01:18 jsg Exp $ */ +/* $OpenBSD: cpufunc.h,v 1.6 2023/08/21 20:17:30 miod Exp $ */ /*- * Copyright (c) 2014 Andrew Turner @@ -99,9 +99,5 @@ load_satp(uint64_t val) __asm volatile("csrw satp, %0" :: "r"(val)); } -#define cpufunc_nullop() riscv_nullop() - -void riscv_nullop(void); - #endif /* _KERNEL */ #endif /* _MACHINE_CPUFUNC_H_ */ diff --git a/sys/arch/riscv64/riscv64/cpufunc_asm.S b/sys/arch/riscv64/riscv64/cpufunc_asm.S deleted file mode 100644 index 9817b307bdd..00000000000 --- a/sys/arch/riscv64/riscv64/cpufunc_asm.S +++ /dev/null @@ -1,43 +0,0 @@ -/* $OpenBSD: cpufunc_asm.S,v 1.3 2021/06/28 18:53:10 deraadt Exp $ */ - -/*- - * Copyright (c) 2015-2017 Ruslan Bukin - * All rights reserved. - * - * Portions of this software were developed by SRI International and the - * University of Cambridge Computer Laboratory under DARPA/AFRL contract - * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme. - * - * Portions of this software were developed by the University of Cambridge - * Computer Laboratory as part of the CTSRD Project, with support from the - * UK Higher Education Innovation Fund (HEIF). - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include - - .text - -ENTRY(riscv_nullop) - ret -END(riscv_nullop) -- 2.20.1