From ce14cb30ad37a319aced808f8953f8538d6fa1bf Mon Sep 17 00:00:00 2001 From: patrick Date: Mon, 18 Dec 2017 18:42:33 +0000 Subject: [PATCH] Read RAM size for chips with SOCRAM like the BCM4334 on one of my Intel machines. --- sys/dev/ic/bwfmreg.h | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/sys/dev/ic/bwfmreg.h b/sys/dev/ic/bwfmreg.h index d84e736a8d8..4df55831b7c 100644 --- a/sys/dev/ic/bwfmreg.h +++ b/sys/dev/ic/bwfmreg.h @@ -1,4 +1,4 @@ -/* $OpenBSD: bwfmreg.h,v 1.11 2017/12/18 16:33:37 patrick Exp $ */ +/* $OpenBSD: bwfmreg.h,v 1.12 2017/12/18 18:42:33 patrick Exp $ */ /* * Copyright (c) 2010-2016 Broadcom Corporation * Copyright (c) 2016,2017 Patrick Wildt @@ -88,7 +88,7 @@ /* CR4 registers */ #define BWFM_ARMCR4_CAP 0x0004 -#define BWFM_ARMCR4_CAP_TCBANB_MASK 0x0f +#define BWFM_ARMCR4_CAP_TCBANB_MASK 0xf #define BWFM_ARMCR4_CAP_TCBANB_SHIFT 0 #define BWFM_ARMCR4_CAP_TCBBNB_MASK 0xf0 #define BWFM_ARMCR4_CAP_TCBBNB_SHIFT 4 @@ -99,7 +99,23 @@ #define BWFM_ARMCR4_BANKPDA 0x004C /* SOCRAM registers */ +#define BWFM_SOCRAM_COREINFO 0x0000 +#define BWFM_SOCRAM_COREINFO_SRBSZ_BASE 14 +#define BWFM_SOCRAM_COREINFO_SRBSZ_MASK 0xf +#define BWFM_SOCRAM_COREINFO_SRBSZ_SHIFT 0 +#define BWFM_SOCRAM_COREINFO_SRNB_MASK 0xf0 +#define BWFM_SOCRAM_COREINFO_SRNB_SHIFT 4 +#define BWFM_SOCRAM_COREINFO_LSS_MASK 0xf00000 +#define BWFM_SOCRAM_COREINFO_LSS_SHIFT 20 #define BWFM_SOCRAM_BANKIDX 0x0010 +#define BWFM_SOCRAM_BANKIDX_MEMTYPE_RAM 0 +#define BWFM_SOCRAM_BANKIDX_MEMTYPE_ROM 1 +#define BWFM_SOCRAM_BANKIDX_MEMTYPE_DEVRAM 2 +#define BWFM_SOCRAM_BANKIDX_MEMTYPE_SHIFT 8 +#define BWFM_SOCRAM_BANKINFO 0x0040 +#define BWFM_SOCRAM_BANKINFO_SZBASE 8192 +#define BWFM_SOCRAM_BANKINFO_SZMASK 0x7f +#define BWFM_SOCRAM_BANKINFO_RETNTRAM_MASK 0x10000 #define BWFM_SOCRAM_BANKPDA 0x0044 /* SDPCMD registers */ -- 2.20.1