From c606b951c7c79ace3dec221729bbb579d4f0c5ec Mon Sep 17 00:00:00 2001 From: miod Date: Tue, 16 Jun 2015 18:24:38 +0000 Subject: [PATCH] Clear the PIC `write request' memory at initialization time. There is apparently a risk of spurious parity errors if we don't. --- sys/arch/sgi/xbow/xbridge.c | 19 +++++- sys/arch/sgi/xbow/xbridgereg.h | 114 ++++++++++++++++++--------------- 2 files changed, 80 insertions(+), 53 deletions(-) diff --git a/sys/arch/sgi/xbow/xbridge.c b/sys/arch/sgi/xbow/xbridge.c index 6f61461c3a1..22f3301733b 100644 --- a/sys/arch/sgi/xbow/xbridge.c +++ b/sys/arch/sgi/xbow/xbridge.c @@ -1,4 +1,4 @@ -/* $OpenBSD: xbridge.c,v 1.94 2015/03/23 20:50:21 miod Exp $ */ +/* $OpenBSD: xbridge.c,v 1.95 2015/06/16 18:24:38 miod Exp $ */ /* * Copyright (c) 2008, 2009, 2011 Miodrag Vallat. @@ -1755,6 +1755,7 @@ xbridge_device_to_pa(bus_addr_t addr) const char * xbridge_setup(struct xbpci_softc *xb) { + bus_addr_t ba; paddr_t pa; uint64_t status, ctrl, int_addr, dirmap; int mode, speed, dev; @@ -1885,6 +1886,22 @@ xbridge_setup(struct xbpci_softc *xb) } } + /* + * Clear the write request memory in PIC, to avoid risking + * spurious parity errors if it is not clean. + */ + if (ISSET(xb->xb_flags, XF_PIC)) { + for (ba = PIC_WR_REQ_LOWER(0); + ba != PIC_WR_REQ_LOWER(PIC_WR_REQ_ENTRIES); ba += 8) + xbridge_write_reg(xb, ba, 0ULL); + for (ba = PIC_WR_REQ_UPPER(0); + ba != PIC_WR_REQ_UPPER(PIC_WR_REQ_ENTRIES); ba += 8) + xbridge_write_reg(xb, ba, 0ULL); + for (ba = PIC_WR_REQ_PARITY(0); + ba != PIC_WR_REQ_PARITY(PIC_WR_REQ_ENTRIES); ba += 8) + xbridge_write_reg(xb, ba, 0ULL); + } + /* * Setup interrupt handling. * diff --git a/sys/arch/sgi/xbow/xbridgereg.h b/sys/arch/sgi/xbow/xbridgereg.h index b6bffde0ac8..b345b624623 100644 --- a/sys/arch/sgi/xbow/xbridgereg.h +++ b/sys/arch/sgi/xbow/xbridgereg.h @@ -1,4 +1,4 @@ -/* $OpenBSD: xbridgereg.h,v 1.14 2014/08/19 19:04:07 miod Exp $ */ +/* $OpenBSD: xbridgereg.h,v 1.15 2015/06/16 18:24:38 miod Exp $ */ /* * Copyright (c) 2008, 2009 Miodrag Vallat. @@ -24,14 +24,14 @@ #define BRIDGE_REGISTERS_SIZE 0x00030000 #define BRIDGE_BUS_OFFSET 0x00800000 -#define BRIDGE_NBUSES 1 -#define PIC_NBUSES 2 +#define BRIDGE_NBUSES 1 +#define PIC_NBUSES 2 -#define BRIDGE_NSLOTS 8 -#define PIC_NSLOTS 4 -#define MAX_SLOTS BRIDGE_NSLOTS +#define BRIDGE_NSLOTS 8 +#define PIC_NSLOTS 4 +#define MAX_SLOTS BRIDGE_NSLOTS -#define BRIDGE_NINTRS 8 +#define BRIDGE_NINTRS 8 #define PIC_WIDGET_STATUS_PCIX_SPEED_MASK 0x0000000c00000000UL #define PIC_WIDGET_STATUS_PCIX_SPEED_SHIFT 34 @@ -60,25 +60,25 @@ #define BRIDGE_DIR_MAP 0x00000080 -#define BRIDGE_DIRMAP_WIDGET_SHIFT 20 -#define BRIDGE_DIRMAP_ADD_512MB 0x00020000 /* add 512MB */ -#define BRIDGE_DIRMAP_BASE_MASK 0x0001ffff -#define BRIDGE_DIRMAP_BASE_SHIFT 31 +#define BRIDGE_DIRMAP_WIDGET_SHIFT 20 +#define BRIDGE_DIRMAP_ADD_512MB 0x00020000 /* add 512MB */ +#define BRIDGE_DIRMAP_BASE_MASK 0x0001ffff +#define BRIDGE_DIRMAP_BASE_SHIFT 31 -#define BRIDGE_PCI0_MEM_SPACE_BASE 0x0000000040000000ULL -#define BRIDGE_PCI_MEM_SPACE_LENGTH 0x0000000040000000ULL -#define BRIDGE_PCI1_MEM_SPACE_BASE 0x00000000c0000000ULL -#define BRIDGE_PCI_IO_SPACE_BASE 0x0000000100000000ULL -#define BRIDGE_PCI_IO_SPACE_LENGTH 0x0000000100000000ULL +#define BRIDGE_PCI0_MEM_SPACE_BASE 0x0000000040000000ULL +#define BRIDGE_PCI_MEM_SPACE_LENGTH 0x0000000040000000ULL +#define BRIDGE_PCI1_MEM_SPACE_BASE 0x00000000c0000000ULL +#define BRIDGE_PCI_IO_SPACE_BASE 0x0000000100000000ULL +#define BRIDGE_PCI_IO_SPACE_LENGTH 0x0000000100000000ULL #define BRIDGE_NIC 0x000000b0 #define BRIDGE_BUS_TIMEOUT 0x000000c0 -#define BRIDGE_BUS_PCI_RETRY_CNT_SHIFT 0 -#define BRIDGE_BUS_PCI_RETRY_CNT_MASK 0x000003ff -#define BRIDGE_BUS_GIO_TIMEOUT 0x00001000 -#define BRIDGE_BUS_PCI_RETRY_HOLD_SHIFT 16 -#define BRIDGE_BUS_PCI_RETRY_HOLD_MASK 0x001f0000 +#define BRIDGE_BUS_PCI_RETRY_CNT_SHIFT 0 +#define BRIDGE_BUS_PCI_RETRY_CNT_MASK 0x000003ff +#define BRIDGE_BUS_GIO_TIMEOUT 0x00001000 +#define BRIDGE_BUS_PCI_RETRY_HOLD_SHIFT 16 +#define BRIDGE_BUS_PCI_RETRY_HOLD_MASK 0x001f0000 #define BRIDGE_PCI_CFG 0x000000c8 #define BRIDGE_PCI_ERR_UPPER 0x000000d0 @@ -189,14 +189,14 @@ * being cleared in groups) */ -#define BRIDGE_ICR_MULTIPLE 0x00000040 -#define BRIDGE_ICR_CRP 0x00000020 -#define BRIDGE_ICR_RESP_BUF 0x00000010 -#define BRIDGE_ICR_REQ_DSP 0x00000008 -#define BRIDGE_ICR_LLP 0x00000004 -#define BRIDGE_ICR_SSRAM 0x00000002 -#define BRIDGE_ICR_PCI 0x00000001 -#define BRIDGE_ICR_ALL 0x0000007f +#define BRIDGE_ICR_MULTIPLE 0x00000040 +#define BRIDGE_ICR_CRP 0x00000020 +#define BRIDGE_ICR_RESP_BUF 0x00000010 +#define BRIDGE_ICR_REQ_DSP 0x00000008 +#define BRIDGE_ICR_LLP 0x00000004 +#define BRIDGE_ICR_SSRAM 0x00000002 +#define BRIDGE_ICR_PCI 0x00000001 +#define BRIDGE_ICR_ALL 0x0000007f /* * PCI Resource Mapping control @@ -268,38 +268,48 @@ #define BRIDGE_RRB_EVEN 0x00000280 #define BRIDGE_RRB_ODD 0x00000288 -#define RRB_VALID 0x8 -#define RRB_VCHAN 0x4 -#define RRB_DEVICE_MASK 0x3 -#define RRB_SHIFT 4 +#define RRB_VALID 0x8 +#define RRB_VCHAN 0x4 +#define RRB_DEVICE_MASK 0x3 +#define RRB_SHIFT 4 /* * Address Translation Entries */ -#define BRIDGE_INTERNAL_ATE 128 -#define XBRIDGE_INTERNAL_ATE 1024 +#define BRIDGE_INTERNAL_ATE 128 +#define XBRIDGE_INTERNAL_ATE 1024 -#define BRIDGE_ATE_SSHIFT 12 /* 4KB */ -#define BRIDGE_ATE_LSHIFT 14 /* 16KB */ -#define BRIDGE_ATE_SSIZE (1ULL << BRIDGE_ATE_SSHIFT) -#define BRIDGE_ATE_LSIZE (1ULL << BRIDGE_ATE_LSHIFT) -#define BRIDGE_ATE_SMASK (BRIDGE_ATE_SSIZE - 1) -#define BRIDGE_ATE_LMASK (BRIDGE_ATE_LSIZE - 1) +#define BRIDGE_ATE_SSHIFT 12 /* 4KB */ +#define BRIDGE_ATE_LSHIFT 14 /* 16KB */ +#define BRIDGE_ATE_SSIZE (1ULL << BRIDGE_ATE_SSHIFT) +#define BRIDGE_ATE_LSIZE (1ULL << BRIDGE_ATE_LSHIFT) +#define BRIDGE_ATE_SMASK (BRIDGE_ATE_SSIZE - 1) +#define BRIDGE_ATE_LMASK (BRIDGE_ATE_LSIZE - 1) #define BRIDGE_ATE(a) (0x00010000 + (a) * 8) -#define ATE_NV 0x0000000000000000ULL -#define ATE_V 0x0000000000000001ULL -#define ATE_COH 0x0000000000000002ULL -#define ATE_PRECISE 0x0000000000000004ULL -#define ATE_PREFETCH 0x0000000000000008ULL -#define ATE_BARRIER 0x0000000000000010ULL -#define ATE_BSWAP 0x0000000000000020ULL /* XBridge */ -#define ATE_WIDGET_MASK 0x0000000000000f00ULL -#define ATE_WIDGET_SHIFT 8 -#define ATE_ADDRESS_MASK 0x0000fffffffff000ULL -#define ATE_RMF_MASK 0x00ff000000000000ULL /* Bridge */ +#define ATE_NV 0x0000000000000000ULL +#define ATE_V 0x0000000000000001ULL +#define ATE_COH 0x0000000000000002ULL +#define ATE_PRECISE 0x0000000000000004ULL +#define ATE_PREFETCH 0x0000000000000008ULL +#define ATE_BARRIER 0x0000000000000010ULL +#define ATE_BSWAP 0x0000000000000020ULL /* XB */ +#define ATE_WIDGET_MASK 0x0000000000000f00ULL +#define ATE_WIDGET_SHIFT 8 +#define ATE_ADDRESS_MASK 0x0000fffffffff000ULL +#define ATE_RMF_MASK 0x00ff000000000000ULL /* BR */ + +/* + * PIC Write Request memory + */ + +#define PIC_WR_REQ_LOWER(a) (0x00018000 + (a) * 8) +#define PIC_WR_REQ_UPPER(a) (0x00018800 + (a) * 8) +#define PIC_WR_REQ_PARITY(a) (0x00019000 + (a) * 8) + +#define PIC_WR_REQ_ENTRIES 0x100 /* * Configuration space -- 2.20.1