From c2bb731dbf823d1f9e12a11cbaef62ff031e740e Mon Sep 17 00:00:00 2001 From: jsg Date: Wed, 13 Sep 2023 12:44:35 +0000 Subject: [PATCH] drm/amd/display: Guard DCN31 PHYD32CLK logic against chip family From George Shen faa77cf5f28f4bbfbbb00f7e0caa2c8561f7dfe0 in linux-6.1.y/6.1.53 25b054c3c89cb6a7106a7982f0f70e83d0797dab in mainline linux --- sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_dccg.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_dccg.c b/sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_dccg.c index cef32a1f91c..b735e548e26 100644 --- a/sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_dccg.c +++ b/sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_dccg.c @@ -84,7 +84,8 @@ static enum phyd32clk_clock_source get_phy_mux_symclk( struct dcn_dccg *dccg_dcn, enum phyd32clk_clock_source src) { - if (dccg_dcn->base.ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) { + if (dccg_dcn->base.ctx->asic_id.chip_family == FAMILY_YELLOW_CARP && + dccg_dcn->base.ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) { if (src == PHYD32CLKC) src = PHYD32CLKF; if (src == PHYD32CLKD) -- 2.20.1