From b7fc37260dec1abafac561a236e97cdb25b2d3c9 Mon Sep 17 00:00:00 2001 From: stsp Date: Sat, 11 Nov 2023 16:50:25 +0000 Subject: [PATCH] Attach dwqe(4) to Intel Elkhart Lake PSE SGMII devices. Patch by msaitoh@netbsd, who tested both PSE SGMII ports on a Helix 330. --- sys/dev/ic/dwqevar.h | 3 ++- sys/dev/pci/if_dwqe_pci.c | 16 ++++++++++++---- 2 files changed, 14 insertions(+), 5 deletions(-) diff --git a/sys/dev/ic/dwqevar.h b/sys/dev/ic/dwqevar.h index c5c7df5caa9..c4a8f138a05 100644 --- a/sys/dev/ic/dwqevar.h +++ b/sys/dev/ic/dwqevar.h @@ -1,4 +1,4 @@ -/* $OpenBSD: dwqevar.h,v 1.9 2023/10/11 12:52:00 stsp Exp $ */ +/* $OpenBSD: dwqevar.h,v 1.10 2023/11/11 16:50:25 stsp Exp $ */ /* * Copyright (c) 2008, 2019 Mark Kettenis * Copyright (c) 2017, 2022 Patrick Wildt @@ -22,6 +22,7 @@ enum dwqe_phy_mode { DWQE_PHY_MODE_RGMII_ID, DWQE_PHY_MODE_RGMII_TXID, DWQE_PHY_MODE_RGMII_RXID, + DWQE_PHY_MODE_SGMII, }; struct dwqe_buf { diff --git a/sys/dev/pci/if_dwqe_pci.c b/sys/dev/pci/if_dwqe_pci.c index 02c28ae711a..e87e7a87160 100644 --- a/sys/dev/pci/if_dwqe_pci.c +++ b/sys/dev/pci/if_dwqe_pci.c @@ -1,4 +1,4 @@ -/* $OpenBSD: if_dwqe_pci.c,v 1.2 2023/10/31 05:46:36 jsg Exp $ */ +/* $OpenBSD: if_dwqe_pci.c,v 1.3 2023/11/11 16:50:25 stsp Exp $ */ /* * Copyright (c) 2023 Stefan Sperling @@ -41,13 +41,13 @@ static const struct pci_matchid dwqe_pci_devices[] = { { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EHL_PSE0_RGMII_1G }, -#if 0 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EHL_PSE0_SGMII_1G }, { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EHL_PSE0_SGMII_2G }, +#if 0 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EHL_PSE1_RGMII_1G }, +#endif { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EHL_PSE1_SGMII_1G }, { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EHL_PSE1_SGMII_2G }, -#endif }; struct dwqe_pci_softc { @@ -107,7 +107,15 @@ dwqe_pci_attach(struct device *parent, struct device *self, void *aux) switch (PCI_PRODUCT(pa->pa_id)) { case PCI_PRODUCT_INTEL_EHL_PSE0_RGMII_1G: sc->sc_phy_mode = DWQE_PHY_MODE_RGMII_ID; - sc->sc_clk = GMAC_MAC_MDIO_ADDR_CR_250_300; + sc->sc_clk = GMAC_MAC_MDIO_ADDR_CR_250_300; + sc->sc_clkrate = 200000000; + break; + case PCI_PRODUCT_INTEL_EHL_PSE0_SGMII_1G: + case PCI_PRODUCT_INTEL_EHL_PSE0_SGMII_2G: + case PCI_PRODUCT_INTEL_EHL_PSE1_SGMII_1G: + case PCI_PRODUCT_INTEL_EHL_PSE1_SGMII_2G: + sc->sc_phy_mode = DWQE_PHY_MODE_SGMII; + sc->sc_clk = GMAC_MAC_MDIO_ADDR_CR_250_300; sc->sc_clkrate = 200000000; break; default: -- 2.20.1