From b70fbf0aabe35ca3688442f607fd7c47cce755ab Mon Sep 17 00:00:00 2001
From: guenther <guenther@openbsd.org>
Date: Thu, 27 Jul 2023 01:51:35 +0000
Subject: [PATCH] Report speculation control bits in dmesg cpu lines.

ok mlarkin@
---
 sys/arch/amd64/amd64/identcpu.c     | 52 ++++++++++++++++++++++++-----
 sys/arch/amd64/include/specialreg.h |  4 ++-
 2 files changed, 47 insertions(+), 9 deletions(-)

diff --git a/sys/arch/amd64/amd64/identcpu.c b/sys/arch/amd64/amd64/identcpu.c
index 7904058a84f..ed8701172d2 100644
--- a/sys/arch/amd64/amd64/identcpu.c
+++ b/sys/arch/amd64/amd64/identcpu.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: identcpu.c,v 1.134 2023/07/21 04:04:51 guenther Exp $	*/
+/*	$OpenBSD: identcpu.c,v 1.135 2023/07/27 01:51:35 guenther Exp $	*/
 /*	$NetBSD: identcpu.c,v 1.1 2003/04/26 18:39:28 fvdl Exp $	*/
 
 /*
@@ -230,18 +230,47 @@ const struct {
 }, cpu_cpuid_apmi_edx[] = {
 	{ CPUIDEDX_ITSC,	"ITSC" },
 }, cpu_amdspec_ebxfeatures[] = {
-	{ CPUIDEBX_IBPB,	"IBPB" },
-	{ CPUIDEBX_IBRS,	"IBRS" },
-	{ CPUIDEBX_STIBP,	"STIBP" },
-	{ CPUIDEBX_SSBD,	"SSBD" },
-	{ CPUIDEBX_VIRT_SSBD,	"VIRTSSBD" },
-	{ CPUIDEBX_SSBD_NOTREQ,	"SSBDNR" },
+	{ CPUIDEBX_INVLPGB,		"INVLPGB" },
+	{ CPUIDEBX_IBPB,		"IBPB" },
+	{ CPUIDEBX_IBRS,		"IBRS" },
+	{ CPUIDEBX_STIBP,		"STIBP" },
+	{ CPUIDEBX_IBRS_ALWAYSON,	"IBRS_ALL" },
+	{ CPUIDEBX_STIBP_ALWAYSON,	"STIBP_ALL" },
+	{ CPUIDEBX_IBRS_PREF,		"IBRS_PREF" },
+	{ CPUIDEBX_IBRS_SAME_MODE,	"IBRS_SM" },
+	{ CPUIDEBX_SSBD,		"SSBD" },
+	{ CPUIDEBX_VIRT_SSBD,		"VIRTSSBD" },
+	{ CPUIDEBX_SSBD_NOTREQ,		"SSBDNR" },
 }, cpu_xsave_extfeatures[] = {
 	{ XSAVE_XSAVEOPT,	"XSAVEOPT" },
 	{ XSAVE_XSAVEC,		"XSAVEC" },
 	{ XSAVE_XGETBV1,	"XGETBV1" },
 	{ XSAVE_XSAVES,		"XSAVES" },
 	{ XSAVE_XFD,		"XFD" },
+}, cpu_arch_cap_features[] = {
+	/* ARCH_CAP_RDCL_NO (not printed) == !MELTDOWN */
+	{ ARCH_CAP_IBRS_ALL,		"IBRS_ALL" },
+	{ ARCH_CAP_RSBA,		"RSBA" },
+	{ ARCH_CAP_SKIP_L1DFL_VMENTRY,	"SKIP_L1DFL" },
+	{ ARCH_CAP_SSB_NO,		"SSB_NO" },
+	{ ARCH_CAP_MDS_NO,		"MDS_NO" },
+	{ ARCH_CAP_IF_PSCHANGE_MC_NO,	"IF_PSCHANGE" },
+	{ ARCH_CAP_TSX_CTRL,		"TSX_CTRL" },
+	{ ARCH_CAP_TAA_NO,		"TAA_NO" },
+	{ ARCH_CAP_MCU_CONTROL,		"MCU_CONTROL" },
+	{ ARCH_CAP_MISC_PACKAGE_CTLS,	"MISC_PKG_CT" },
+	{ ARCH_CAP_ENERGY_FILTERING_CTL, "ENERGY_FILT" },
+	{ ARCH_CAP_DOITM,		"DOITM" },
+	{ ARCH_CAP_SBDR_SSDP_NO,	"SBDR_SSDP_N" },
+	{ ARCH_CAP_FBSDP_NO,		"FBSDP_NO" },
+	{ ARCH_CAP_PSDP_NO,		"PSDP_NO" },
+	{ ARCH_CAP_FB_CLEAR,		"FB_CLEAR" },
+	{ ARCH_CAP_FB_CLEAR_CTRL,	"FB_CLEAR_CT" },
+	{ ARCH_CAP_RRSBA,		"RRSBA" },
+	{ ARCH_CAP_BHI_NO,		"BHI_NO" },
+	{ ARCH_CAP_XAPIC_DISABLE_STATUS, "XAPIC_DIS" },
+	{ ARCH_CAP_OVERCLOCKING_STATUS,	"OVERCLOCK" },
+	{ ARCH_CAP_PBRSB_NO,		"PBRSB_NO" },
 };
 
 int
@@ -674,7 +703,7 @@ identifycpu(struct cpu_info *ci)
 			ci->ci_feature_tpmflags |= TPM_ARAT;
 	}
 
-	/* AMD speculation control features */
+	/* speculation control features */
 	if (!strcmp(cpu_vendor, "AuthenticAMD")) {
 		if (ci->ci_pnfeatset >= 0x80000008) {
 			CPUID(0x80000008, dummy, ci->ci_feature_amdspec_ebx,
@@ -685,6 +714,13 @@ identifycpu(struct cpu_info *ci)
 					printf(",%s",
 					    cpu_amdspec_ebxfeatures[i].str);
 		}
+	} else if (!strcmp(cpu_vendor, "GenuineIntel") &&
+	    (ci->ci_feature_sefflags_edx & SEFF0EDX_ARCH_CAP)) {
+		uint64_t msr = rdmsr(MSR_ARCH_CAPABILITIES);
+
+		for (i = 0; i < nitems(cpu_arch_cap_features); i++)
+			if (msr & cpu_arch_cap_features[i].bit)
+				printf(",%s", cpu_arch_cap_features[i].str);
 	}
 
 	/* xsave subfeatures */
diff --git a/sys/arch/amd64/include/specialreg.h b/sys/arch/amd64/include/specialreg.h
index db5d02aeedb..a5c516a8d3e 100644
--- a/sys/arch/amd64/include/specialreg.h
+++ b/sys/arch/amd64/include/specialreg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: specialreg.h,v 1.105 2023/07/24 14:54:00 deraadt Exp $	*/
+/*	$OpenBSD: specialreg.h,v 1.106 2023/07/27 01:51:35 guenther Exp $	*/
 /*	$NetBSD: specialreg.h,v 1.1 2003/04/26 18:39:48 fvdl Exp $	*/
 /*	$NetBSD: x86/specialreg.h,v 1.2 2003/04/25 21:54:30 fvdl Exp $	*/
 
@@ -334,12 +334,14 @@
 /*
  * AMD CPUID function 0x80000008 EBX bits
  */
+#define CPUIDEBX_INVLPGB	(1ULL <<  3)	/* INVLPG w/broadcast */
 #define CPUIDEBX_IBPB		(1ULL << 12)	/* Speculation Control IBPB */
 #define CPUIDEBX_IBRS		(1ULL << 14)	/* Speculation Control IBRS */
 #define CPUIDEBX_STIBP		(1ULL << 15)	/* Speculation Control STIBP */
 #define CPUIDEBX_IBRS_ALWAYSON	(1ULL << 16)	/* IBRS always on mode */
 #define CPUIDEBX_STIBP_ALWAYSON	(1ULL << 17)	/* STIBP always on mode */
 #define CPUIDEBX_IBRS_PREF	(1ULL << 18)	/* IBRS preferred */
+#define CPUIDEBX_IBRS_SAME_MODE	(1ULL << 19)	/* IBRS not mode-specific */
 #define CPUIDEBX_SSBD		(1ULL << 24)	/* Speculation Control SSBD */
 #define CPUIDEBX_VIRT_SSBD	(1ULL << 25)	/* Virt Spec Control SSBD */
 #define CPUIDEBX_SSBD_NOTREQ	(1ULL << 26)	/* SSBD not required */
-- 
2.20.1