From b4278f973261d42825abefb66d873cbbffde0b68 Mon Sep 17 00:00:00 2001 From: jsg Date: Tue, 13 Jun 2023 02:40:37 +0000 Subject: [PATCH] drm/amd/display: Add missing WA and MCLK validation From Rodrigo Siqueira 374f7fa01ae56bc000dc1d54e80a8f4e7f606028 in linux-6.1.y/6.1.29 822b84ecfc646da0f87fd947fa00dc3be5e45ecc in mainline linux --- .../pci/drm/amd/display/dc/dcn32/dcn32_hwseq.c | 1 + .../drm/amd/display/dc/dcn32/dcn32_resource.c | 2 +- .../drm/amd/display/dc/dml/dcn30/dcn30_fpu.c | 18 +++++++++++++++++- 3 files changed, 19 insertions(+), 2 deletions(-) diff --git a/sys/dev/pci/drm/amd/display/dc/dcn32/dcn32_hwseq.c b/sys/dev/pci/drm/amd/display/dc/dcn32/dcn32_hwseq.c index 816dcb33b24..6ff88a81d22 100644 --- a/sys/dev/pci/drm/amd/display/dc/dcn32/dcn32_hwseq.c +++ b/sys/dev/pci/drm/amd/display/dc/dcn32/dcn32_hwseq.c @@ -984,6 +984,7 @@ void dcn32_init_hw(struct dc *dc) if (dc->ctx->dmub_srv) { dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv->dmub); dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr; + dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch; } /* Enable support for ODM and windowed MPO if policy flag is set */ diff --git a/sys/dev/pci/drm/amd/display/dc/dcn32/dcn32_resource.c b/sys/dev/pci/drm/amd/display/dc/dcn32/dcn32_resource.c index a942e281218..903f80a8c20 100644 --- a/sys/dev/pci/drm/amd/display/dc/dcn32/dcn32_resource.c +++ b/sys/dev/pci/drm/amd/display/dc/dcn32/dcn32_resource.c @@ -1984,7 +1984,7 @@ int dcn32_populate_dml_pipes_from_context( // In general cases we want to keep the dram clock change requirement // (prefer configs that support MCLK switch). Only override to false // for SubVP - if (subvp_in_use) + if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || subvp_in_use) context->bw_ctx.dml.soc.dram_clock_change_requirement_final = false; else context->bw_ctx.dml.soc.dram_clock_change_requirement_final = true; diff --git a/sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c b/sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c index 4fa63636479..fdfb19337ea 100644 --- a/sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c +++ b/sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c @@ -368,7 +368,9 @@ void dcn30_fpu_update_soc_for_wm_a(struct dc *dc, struct dc_state *context) dc_assert_fp_enabled(); if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid) { - context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us; + if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || + context->bw_ctx.dml.soc.dram_clock_change_latency_us == 0) + context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us; context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us; context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us; } @@ -520,6 +522,20 @@ void dcn30_fpu_calculate_wm_and_dlg( pipe_idx++; } + // WA: restrict FPO to use first non-strobe mode (NV24 BW issue) + if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching && + dc->dml.soc.num_chans <= 4 && + context->bw_ctx.dml.vba.DRAMSpeed <= 1700 && + context->bw_ctx.dml.vba.DRAMSpeed >= 1500) { + + for (i = 0; i < dc->dml.soc.num_states; i++) { + if (dc->dml.soc.clock_limits[i].dram_speed_mts > 1700) { + context->bw_ctx.dml.vba.DRAMSpeed = dc->dml.soc.clock_limits[i].dram_speed_mts; + break; + } + } + } + dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel); if (!pstate_en) -- 2.20.1