From b0b1e4bd690096946613dbc30b72d4ee90aa2985 Mon Sep 17 00:00:00 2001 From: cheloha Date: Fri, 14 May 2021 16:44:38 +0000 Subject: [PATCH] amd64: specialreg.h: add MSR_TSC_ADJUST Where available, the IA32_TSC_ADJUST MSR may be used to make race-free relative adjustments to a logical CPU's TSC. The value in the register is interpreted as a signed 64-bit offset and added to the "real" value of the TSC whenever the TSC MSR is read. That is: RDTSC = REAL_TSC + TSC_ADJUST and: RDMSR TSC = REAL_TSC + TSC_ADJUST For example, if REAL_TSC=1 and TSC_ADJUST=1, then RDTSC would yield 2. Or if REAL_TSC=10 and TSC_ADJUST=-5, then RDTSC would yield 5. Writing TSC_ADJUST does not change the "real" underlying value of the TSC. Said another way setting TSC_ADJUST to zero will always undo any prior adjustment. This property may be useful in fixing desynchronized TSCs. In particular, buggy firmware may erroneously desynchronize a normally synchronized TSC. If this happens, in theory we can do: wrmsr(MSR_TSC_ADJUST, 0); and fix any desynchronization during boot/resume with no fuss. ok mlarkin@ --- sys/arch/amd64/include/specialreg.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/sys/arch/amd64/include/specialreg.h b/sys/arch/amd64/include/specialreg.h index 2d64a12a784..da9907fb370 100644 --- a/sys/arch/amd64/include/specialreg.h +++ b/sys/arch/amd64/include/specialreg.h @@ -1,4 +1,4 @@ -/* $OpenBSD: specialreg.h,v 1.89 2021/03/29 12:39:02 dv Exp $ */ +/* $OpenBSD: specialreg.h,v 1.90 2021/05/14 16:44:38 cheloha Exp $ */ /* $NetBSD: specialreg.h,v 1.1 2003/04/26 18:39:48 fvdl Exp $ */ /* $NetBSD: x86/specialreg.h,v 1.2 2003/04/25 21:54:30 fvdl Exp $ */ @@ -352,6 +352,7 @@ #define MSR_EBC_FREQUENCY_ID 0x02c /* Pentium 4 only */ #define MSR_TEST_CTL 0x033 #define MSR_IA32_FEATURE_CONTROL 0x03a +#define MSR_TSC_ADJUST 0x03b #define MSR_SPEC_CTRL 0x048 /* Speculation Control IBRS / STIBP */ #define SPEC_CTRL_IBRS (1ULL << 0) #define SPEC_CTRL_STIBP (1ULL << 1) -- 2.20.1