From a955d53b92aa94a3ab098e482ab277a6c0393891 Mon Sep 17 00:00:00 2001 From: kettenis Date: Sat, 15 Jul 2023 19:35:53 +0000 Subject: [PATCH] Implement PAC support. ok patrick@ --- .../Plugins/ABI/AArch64/ABISysV_arm64.cpp | 35 +++++ .../NativeRegisterContextOpenBSD_arm64.cpp | 125 ++++++------------ .../NativeRegisterContextOpenBSD_arm64.h | 8 +- .../Process/elf-core/RegisterUtilities.h | 2 + 4 files changed, 88 insertions(+), 82 deletions(-) diff --git a/gnu/llvm/lldb/source/Plugins/ABI/AArch64/ABISysV_arm64.cpp b/gnu/llvm/lldb/source/Plugins/ABI/AArch64/ABISysV_arm64.cpp index 16fb38e107c..e37fbec9ea3 100644 --- a/gnu/llvm/lldb/source/Plugins/ABI/AArch64/ABISysV_arm64.cpp +++ b/gnu/llvm/lldb/source/Plugins/ABI/AArch64/ABISysV_arm64.cpp @@ -813,6 +813,31 @@ static lldb::addr_t ReadLinuxProcessAddressMask(lldb::ProcessSP process_sp, return address_mask; } +// Reads code or data address mask for the current OpenBSD process. +static lldb::addr_t ReadOpenBSDProcessAddressMask(lldb::ProcessSP process_sp, + llvm::StringRef reg_name) { + // We set default value of mask such that no bits are masked out. + uint64_t address_mask = 0ULL; + // If Pointer Authentication feature is enabled then OpenBSD exposes + // PAC data and code mask register. Try reading relevant register + // below and merge it with default address mask calculated above. + lldb::ThreadSP thread_sp = process_sp->GetThreadList().GetSelectedThread(); + if (thread_sp) { + lldb::RegisterContextSP reg_ctx_sp = thread_sp->GetRegisterContext(); + if (reg_ctx_sp) { + const RegisterInfo *reg_info = + reg_ctx_sp->GetRegisterInfoByName(reg_name, 0); + if (reg_info) { + lldb::addr_t mask_reg_val = reg_ctx_sp->ReadRegisterAsUnsigned( + reg_info->kinds[eRegisterKindLLDB], LLDB_INVALID_ADDRESS); + if (mask_reg_val != LLDB_INVALID_ADDRESS) + address_mask |= mask_reg_val; + } + } + } + return address_mask; +} + lldb::addr_t ABISysV_arm64::FixCodeAddress(lldb::addr_t pc) { if (lldb::ProcessSP process_sp = GetProcessSP()) { if (process_sp->GetTarget().GetArchitecture().GetTriple().isOSLinux() && @@ -820,6 +845,11 @@ lldb::addr_t ABISysV_arm64::FixCodeAddress(lldb::addr_t pc) { process_sp->SetCodeAddressMask( ReadLinuxProcessAddressMask(process_sp, "code_mask")); + if (process_sp->GetTarget().GetArchitecture().GetTriple().isOSOpenBSD() && + !process_sp->GetCodeAddressMask()) + process_sp->SetCodeAddressMask( + ReadOpenBSDProcessAddressMask(process_sp, "code_mask")); + return FixAddress(pc, process_sp->GetCodeAddressMask()); } return pc; @@ -832,6 +862,11 @@ lldb::addr_t ABISysV_arm64::FixDataAddress(lldb::addr_t pc) { process_sp->SetDataAddressMask( ReadLinuxProcessAddressMask(process_sp, "data_mask")); + if (process_sp->GetTarget().GetArchitecture().GetTriple().isOSOpenBSD() && + !process_sp->GetDataAddressMask()) + process_sp->SetDataAddressMask( + ReadOpenBSDProcessAddressMask(process_sp, "data_mask")); + return FixAddress(pc, process_sp->GetDataAddressMask()); } return pc; diff --git a/gnu/llvm/lldb/source/Plugins/Process/OpenBSD/NativeRegisterContextOpenBSD_arm64.cpp b/gnu/llvm/lldb/source/Plugins/Process/OpenBSD/NativeRegisterContextOpenBSD_arm64.cpp index 8b76bc8bad0..7fe177e49e9 100644 --- a/gnu/llvm/lldb/source/Plugins/Process/OpenBSD/NativeRegisterContextOpenBSD_arm64.cpp +++ b/gnu/llvm/lldb/source/Plugins/Process/OpenBSD/NativeRegisterContextOpenBSD_arm64.cpp @@ -27,6 +27,7 @@ // clang-format off #include +#include #include #include #include @@ -37,77 +38,6 @@ using namespace lldb_private::process_openbsd; #define REG_CONTEXT_SIZE (GetGPRSize() + GetFPRSize()) -// ARM64 general purpose registers. -static const uint32_t g_gpr_regnums_arm64[] = { - gpr_x0_arm64, gpr_x1_arm64, gpr_x2_arm64, gpr_x3_arm64, - gpr_x4_arm64, gpr_x5_arm64, gpr_x6_arm64, gpr_x7_arm64, - gpr_x8_arm64, gpr_x9_arm64, gpr_x10_arm64, gpr_x11_arm64, - gpr_x12_arm64, gpr_x13_arm64, gpr_x14_arm64, gpr_x15_arm64, - gpr_x16_arm64, gpr_x17_arm64, gpr_x18_arm64, gpr_x19_arm64, - gpr_x20_arm64, gpr_x21_arm64, gpr_x22_arm64, gpr_x23_arm64, - gpr_x24_arm64, gpr_x25_arm64, gpr_x26_arm64, gpr_x27_arm64, - gpr_x28_arm64, gpr_fp_arm64, gpr_lr_arm64, gpr_sp_arm64, - gpr_pc_arm64, gpr_cpsr_arm64, gpr_w0_arm64, gpr_w1_arm64, - gpr_w2_arm64, gpr_w3_arm64, gpr_w4_arm64, gpr_w5_arm64, - gpr_w6_arm64, gpr_w7_arm64, gpr_w8_arm64, gpr_w9_arm64, - gpr_w10_arm64, gpr_w11_arm64, gpr_w12_arm64, gpr_w13_arm64, - gpr_w14_arm64, gpr_w15_arm64, gpr_w16_arm64, gpr_w17_arm64, - gpr_w18_arm64, gpr_w19_arm64, gpr_w20_arm64, gpr_w21_arm64, - gpr_w22_arm64, gpr_w23_arm64, gpr_w24_arm64, gpr_w25_arm64, - gpr_w26_arm64, gpr_w27_arm64, gpr_w28_arm64, - LLDB_INVALID_REGNUM // register sets need to end with this flag -}; -static_assert(((sizeof g_gpr_regnums_arm64 / sizeof g_gpr_regnums_arm64[0]) - - 1) == k_num_gpr_registers_arm64, - "g_gpr_regnums_arm64 has wrong number of register infos"); - -// ARM64 floating point registers. -static const uint32_t g_fpu_regnums_arm64[] = { - fpu_v0_arm64, fpu_v1_arm64, fpu_v2_arm64, fpu_v3_arm64, - fpu_v4_arm64, fpu_v5_arm64, fpu_v6_arm64, fpu_v7_arm64, - fpu_v8_arm64, fpu_v9_arm64, fpu_v10_arm64, fpu_v11_arm64, - fpu_v12_arm64, fpu_v13_arm64, fpu_v14_arm64, fpu_v15_arm64, - fpu_v16_arm64, fpu_v17_arm64, fpu_v18_arm64, fpu_v19_arm64, - fpu_v20_arm64, fpu_v21_arm64, fpu_v22_arm64, fpu_v23_arm64, - fpu_v24_arm64, fpu_v25_arm64, fpu_v26_arm64, fpu_v27_arm64, - fpu_v28_arm64, fpu_v29_arm64, fpu_v30_arm64, fpu_v31_arm64, - - fpu_s0_arm64, fpu_s1_arm64, fpu_s2_arm64, fpu_s3_arm64, - fpu_s4_arm64, fpu_s5_arm64, fpu_s6_arm64, fpu_s7_arm64, - fpu_s8_arm64, fpu_s9_arm64, fpu_s10_arm64, fpu_s11_arm64, - fpu_s12_arm64, fpu_s13_arm64, fpu_s14_arm64, fpu_s15_arm64, - fpu_s16_arm64, fpu_s17_arm64, fpu_s18_arm64, fpu_s19_arm64, - fpu_s20_arm64, fpu_s21_arm64, fpu_s22_arm64, fpu_s23_arm64, - fpu_s24_arm64, fpu_s25_arm64, fpu_s26_arm64, fpu_s27_arm64, - fpu_s28_arm64, fpu_s29_arm64, fpu_s30_arm64, fpu_s31_arm64, - - fpu_d0_arm64, fpu_d1_arm64, fpu_d2_arm64, fpu_d3_arm64, - fpu_d4_arm64, fpu_d5_arm64, fpu_d6_arm64, fpu_d7_arm64, - fpu_d8_arm64, fpu_d9_arm64, fpu_d10_arm64, fpu_d11_arm64, - fpu_d12_arm64, fpu_d13_arm64, fpu_d14_arm64, fpu_d15_arm64, - fpu_d16_arm64, fpu_d17_arm64, fpu_d18_arm64, fpu_d19_arm64, - fpu_d20_arm64, fpu_d21_arm64, fpu_d22_arm64, fpu_d23_arm64, - fpu_d24_arm64, fpu_d25_arm64, fpu_d26_arm64, fpu_d27_arm64, - fpu_d28_arm64, fpu_d29_arm64, fpu_d30_arm64, fpu_d31_arm64, - fpu_fpsr_arm64, fpu_fpcr_arm64, - LLDB_INVALID_REGNUM // register sets need to end with this flag -}; -static_assert(((sizeof g_fpu_regnums_arm64 / sizeof g_fpu_regnums_arm64[0]) - - 1) == k_num_fpr_registers_arm64, - "g_fpu_regnums_arm64 has wrong number of register infos"); - -namespace { -// Number of register sets provided by this context. -enum { k_num_register_sets = 2 }; -} - -// Register sets for ARM64. -static const RegisterSet g_reg_sets_arm64[k_num_register_sets] = { - {"General Purpose Registers", "gpr", k_num_gpr_registers_arm64, - g_gpr_regnums_arm64}, - {"Floating Point Registers", "fpu", k_num_fpr_registers_arm64, - g_fpu_regnums_arm64}}; - std::unique_ptr NativeRegisterContextOpenBSD::CreateHostNativeRegisterContextOpenBSD( const ArchSpec &target_arch, NativeThreadProtocol &native_thread) { @@ -122,7 +52,9 @@ static RegisterInfoInterface * CreateRegisterInfoInterface(const ArchSpec &target_arch) { assert((HostInfo::GetArchitecture().GetAddressByteSize() == 8) && "Register setting path assumes this is a 64-bit host"); - return new RegisterInfoPOSIX_arm64(target_arch, 0); + + Flags opt_regsets = RegisterInfoPOSIX_arm64::eRegsetMaskPAuth; + return new RegisterInfoPOSIX_arm64(target_arch, opt_regsets); } static llvm::APInt uint128ToAPInt(__uint128_t in) { @@ -145,23 +77,25 @@ NativeRegisterContextOpenBSD_arm64::NativeRegisterContextOpenBSD_arm64( CreateRegisterInfoInterface(target_arch)), m_gpr(), m_fpr() {} -uint32_t NativeRegisterContextOpenBSD_arm64::GetUserRegisterCount() const { - uint32_t count = 0; - for (uint32_t set_index = 0; set_index < k_num_register_sets; ++set_index) - count += g_reg_sets_arm64[set_index].num_registers; - return count; +RegisterInfoPOSIX_arm64 & +NativeRegisterContextOpenBSD_arm64::GetRegisterInfo() const { + return static_cast(*m_register_info_interface_up); } uint32_t NativeRegisterContextOpenBSD_arm64::GetRegisterSetCount() const { - return k_num_register_sets; + return GetRegisterInfo().GetRegisterSetCount(); } const RegisterSet * NativeRegisterContextOpenBSD_arm64::GetRegisterSet(uint32_t set_index) const { - if (set_index < k_num_register_sets) - return &g_reg_sets_arm64[set_index]; + return GetRegisterInfo().GetRegisterSet(set_index); +} - return nullptr; +uint32_t NativeRegisterContextOpenBSD_arm64::GetUserRegisterCount() const { + uint32_t count = 0; + for (uint32_t set_index = 0; set_index < GetRegisterSetCount(); ++set_index) + count += GetRegisterSet(set_index)->num_registers; + return count; } Status @@ -202,6 +136,18 @@ NativeRegisterContextOpenBSD_arm64::ReadRegister(const RegisterInfo *reg_info, return error; } + if (GetRegisterInfo().IsPAuthReg(reg)) { + uint32_t offset; + + offset = reg_info->byte_offset - GetRegisterInfo().GetPAuthOffset(); + reg_value = (uint64_t)m_pacmask[offset > 0]; + if (reg_value.GetByteSize() > reg_info->byte_size) { + reg_value.SetType(reg_info); + } + + return error; + } + switch (reg) { case gpr_x0_arm64: case gpr_x1_arm64: @@ -527,6 +473,8 @@ int NativeRegisterContextOpenBSD_arm64::GetSetForNativeRegNum( return GPRegSet; else if (reg_num >= k_first_fpr_arm64 && reg_num <= k_last_fpr_arm64) return FPRegSet; + else if (GetRegisterInfo().IsPAuthReg(reg_num)) + return PACMaskRegSet; else return -1; } @@ -539,6 +487,9 @@ int NativeRegisterContextOpenBSD_arm64::ReadRegisterSet(uint32_t set) { case FPRegSet: ReadFPR(); return 0; + case PACMaskRegSet: + ReadPACMask(); + return 0; default: break; } @@ -558,4 +509,16 @@ int NativeRegisterContextOpenBSD_arm64::WriteRegisterSet(uint32_t set) { } return -1; } + +Status NativeRegisterContextOpenBSD_arm64::ReadPACMask() { +#ifdef PT_PACMASK + return NativeProcessOpenBSD::PtraceWrapper(PT_PACMASK, GetProcessPid(), + &m_pacmask, sizeof(m_pacmask)); +#else + Status error; + ::memset(&m_pacmask, 0, sizeof(m_pacmask)); + return error; +#endif +} + #endif diff --git a/gnu/llvm/lldb/source/Plugins/Process/OpenBSD/NativeRegisterContextOpenBSD_arm64.h b/gnu/llvm/lldb/source/Plugins/Process/OpenBSD/NativeRegisterContextOpenBSD_arm64.h index 7cab092bdc5..106d1b610b7 100644 --- a/gnu/llvm/lldb/source/Plugins/Process/OpenBSD/NativeRegisterContextOpenBSD_arm64.h +++ b/gnu/llvm/lldb/source/Plugins/Process/OpenBSD/NativeRegisterContextOpenBSD_arm64.h @@ -16,6 +16,7 @@ // clang-format on #include "Plugins/Process/OpenBSD/NativeRegisterContextOpenBSD.h" +#include "Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h" #include "Plugins/Process/Utility/lldb-arm64-register-enums.h" namespace lldb_private { @@ -65,16 +66,21 @@ protected: private: // Private member types. - enum { GPRegSet, FPRegSet }; + enum { GPRegSet, FPRegSet, PACMaskRegSet }; // Private member variables. struct reg m_gpr; struct fpreg m_fpr; + register_t m_pacmask[2]; int GetSetForNativeRegNum(int reg_num) const; int ReadRegisterSet(uint32_t set); int WriteRegisterSet(uint32_t set); + + RegisterInfoPOSIX_arm64 &GetRegisterInfo() const; + + Status ReadPACMask(); }; } // namespace process_openbsd diff --git a/gnu/llvm/lldb/source/Plugins/Process/elf-core/RegisterUtilities.h b/gnu/llvm/lldb/source/Plugins/Process/elf-core/RegisterUtilities.h index f6a2fbdcc93..f911bddb7ad 100644 --- a/gnu/llvm/lldb/source/Plugins/Process/elf-core/RegisterUtilities.h +++ b/gnu/llvm/lldb/source/Plugins/Process/elf-core/RegisterUtilities.h @@ -67,6 +67,7 @@ enum { NT_AUXV = 11, NT_REGS = 20, NT_FPREGS = 21, + NT_PACMASK = 24, }; } @@ -121,6 +122,7 @@ constexpr RegsetDesc AARCH64_SVE_Desc[] = { constexpr RegsetDesc AARCH64_PAC_Desc[] = { {llvm::Triple::Linux, llvm::Triple::aarch64, llvm::ELF::NT_ARM_PAC_MASK}, + {llvm::Triple::OpenBSD, llvm::Triple::aarch64, OPENBSD::NT_PACMASK}, }; constexpr RegsetDesc PPC_VMX_Desc[] = { -- 2.20.1