From a518ac48101d7b919deedee89982e7133760d43e Mon Sep 17 00:00:00 2001 From: jsg Date: Wed, 25 Jan 2023 02:31:13 +0000 Subject: [PATCH] drm/amdgpu/pm: use the specific mailbox registers only for SMU IP v13.0.4 From Tim Huang 703011b41c4f0d333e731edbb632eab62c0e1810 in linux-6.1.y/6.1.8 069a5af97ce3a1448a3566ce8b63b60e51e19958 in mainline linux --- .../drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c b/sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c index 97e1d55dcaa..8fa9a36c38b 100644 --- a/sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c +++ b/sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c @@ -1026,6 +1026,15 @@ static const struct pptable_funcs smu_v13_0_4_ppt_funcs = { .set_gfx_power_up_by_imu = smu_v13_0_set_gfx_power_up_by_imu, }; +static void smu_v13_0_4_set_smu_mailbox_registers(struct smu_context *smu) +{ + struct amdgpu_device *adev = smu->adev; + + smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82); + smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66); + smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); +} + void smu_v13_0_4_set_ppt_funcs(struct smu_context *smu) { struct amdgpu_device *adev = smu->adev; @@ -1035,7 +1044,9 @@ void smu_v13_0_4_set_ppt_funcs(struct smu_context *smu) smu->feature_map = smu_v13_0_4_feature_mask_map; smu->table_map = smu_v13_0_4_table_map; smu->is_apu = true; - smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82); - smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66); - smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); + + if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 4)) + smu_v13_0_4_set_smu_mailbox_registers(smu); + else + smu_v13_0_set_smu_mailbox_registers(smu); } -- 2.20.1