From a1b4c27d63c1f4d69bc2973e2b3564409bbd362f Mon Sep 17 00:00:00 2001 From: jsg Date: Thu, 21 Apr 2022 09:40:40 +0000 Subject: [PATCH] drm/amd/display: FEC check in timing validation From Chiawen Huang 92951699a5f11043b9d1402ea21787f420b36094 in linux 5.15.y/5.15.35 7d56a154e22ffb3613fdebf83ec34d5225a22993 in mainline linux --- sys/dev/pci/drm/amd/display/dc/core/amdgpu_dc.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/sys/dev/pci/drm/amd/display/dc/core/amdgpu_dc.c b/sys/dev/pci/drm/amd/display/dc/core/amdgpu_dc.c index b37c4d2e7a1..35a27fe48f6 100644 --- a/sys/dev/pci/drm/amd/display/dc/core/amdgpu_dc.c +++ b/sys/dev/pci/drm/amd/display/dc/core/amdgpu_dc.c @@ -1377,6 +1377,10 @@ bool dc_validate_seamless_boot_timing(const struct dc *dc, if (!link->link_enc->funcs->is_dig_enabled(link->link_enc)) return false; + /* Check for FEC status*/ + if (link->link_enc->funcs->fec_is_active(link->link_enc)) + return false; + enc_inst = link->link_enc->funcs->get_dig_frontend(link->link_enc); if (enc_inst == ENGINE_ID_UNKNOWN) -- 2.20.1