From 9b181e42174c46b8f6472019ac70975c2bb53ad2 Mon Sep 17 00:00:00 2001 From: jsg Date: Tue, 28 Mar 2023 04:24:27 +0000 Subject: [PATCH] drm/amd/display: Do not set DRR on pipe Commit From Wesley Chalmers f8080f1e300e7abcc03025ec8b5bab69ae98daaa in linux-6.1.y/6.1.21 56574f89dbd84004c3fd6485bcaafb5aa9b8be14 in mainline linux --- sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_hwseq.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_hwseq.c b/sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_hwseq.c index 8c504571126..c20e9f76f02 100644 --- a/sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_hwseq.c +++ b/sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_hwseq.c @@ -992,8 +992,5 @@ void dcn30_prepare_bandwidth(struct dc *dc, dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz); dcn20_prepare_bandwidth(dc, context); - - dc_dmub_srv_p_state_delegate(dc, - context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching, context); } -- 2.20.1