From 8ea71dd1587839264e6c32a4186a86958c8e2d37 Mon Sep 17 00:00:00 2001 From: patrick Date: Mon, 20 Aug 2018 16:48:03 +0000 Subject: [PATCH] Add the i.MX8MQ eCSPI clocks. --- sys/dev/fdt/imxccm.c | 31 ++++++++++++++++++++++++++++++- sys/dev/fdt/imxccm_clocks.h | 30 ++++++++++++++++++++++++++++++ 2 files changed, 60 insertions(+), 1 deletion(-) diff --git a/sys/dev/fdt/imxccm.c b/sys/dev/fdt/imxccm.c index 4679fe6799f..e1e0ddd42cf 100644 --- a/sys/dev/fdt/imxccm.c +++ b/sys/dev/fdt/imxccm.c @@ -1,4 +1,4 @@ -/* $OpenBSD: imxccm.c,v 1.10 2018/08/13 15:15:02 patrick Exp $ */ +/* $OpenBSD: imxccm.c,v 1.11 2018/08/20 16:48:03 patrick Exp $ */ /* * Copyright (c) 2012-2013 Patrick Wildt * @@ -225,6 +225,8 @@ uint32_t imxccm_get_ahbclk(struct imxccm_softc *); uint32_t imxccm_get_ipgclk(struct imxccm_softc *); uint32_t imxccm_get_ipg_perclk(struct imxccm_softc *); uint32_t imxccm_get_uartclk(struct imxccm_softc *); +uint32_t imxccm_imx8mq_ecspi(struct imxccm_softc *sc, uint32_t); +uint32_t imxccm_imx8mq_enet(struct imxccm_softc *sc, uint32_t); uint32_t imxccm_imx8mq_i2c(struct imxccm_softc *sc, uint32_t); uint32_t imxccm_imx8mq_uart(struct imxccm_softc *sc, uint32_t); uint32_t imxccm_imx8mq_usdhc(struct imxccm_softc *sc, uint32_t); @@ -591,6 +593,29 @@ imxccm_imx7d_usdhc(struct imxccm_softc *sc, uint32_t idx) } } +uint32_t +imxccm_imx8mq_ecspi(struct imxccm_softc *sc, uint32_t idx) +{ + uint32_t mux; + + if (idx >= sc->sc_nmuxs || sc->sc_muxs[idx].reg == 0) + return 0; + + mux = HREAD4(sc, sc->sc_muxs[idx].reg); + mux >>= sc->sc_muxs[idx].shift; + mux &= sc->sc_muxs[idx].mask; + + switch (mux) { + case 0: + return clock_get_frequency(sc->sc_node, "osc_25m"); + case 1: + return 200 * 1000 * 1000; /* sys2_pll_200m */ + default: + printf("%s: 0x%08x 0x%08x\n", __func__, idx, mux); + return 0; + } +} + uint32_t imxccm_imx8mq_enet(struct imxccm_softc *sc, uint32_t idx) { @@ -1036,6 +1061,10 @@ imxccm_get_frequency(void *cookie, uint32_t *cells) case IMX8MQ_CLK_USB_CORE_REF_SRC: case IMX8MQ_CLK_USB_PHY_REF_SRC: return imxccm_imx8mq_usb(sc, idx); + case IMX8MQ_CLK_ECSPI1_SRC: + case IMX8MQ_CLK_ECSPI2_SRC: + case IMX8MQ_CLK_ECSPI3_SRC: + return imxccm_imx8mq_ecspi(sc, idx); } } else if (sc->sc_gates == imx7d_gates) { switch (idx) { diff --git a/sys/dev/fdt/imxccm_clocks.h b/sys/dev/fdt/imxccm_clocks.h index 14a5f50ad69..eb60b56dcdc 100644 --- a/sys/dev/fdt/imxccm_clocks.h +++ b/sys/dev/fdt/imxccm_clocks.h @@ -381,6 +381,14 @@ struct imxccm_mux imx7d_muxs[] = { #define IMX8MQ_CLK_USB_PHY_REF_CG 0x12c #define IMX8MQ_CLK_USB_PHY_REF_PRE_DIV 0x12d #define IMX8MQ_CLK_USB_PHY_REF_DIV 0x12e +#define IMX8MQ_CLK_ECSPI1_SRC 0x12f +#define IMX8MQ_CLK_ECSPI1_CG 0x130 +#define IMX8MQ_CLK_ECSPI1_PRE_DIV 0x131 +#define IMX8MQ_CLK_ECSPI1_DIV 0x132 +#define IMX8MQ_CLK_ECSPI2_SRC 0x133 +#define IMX8MQ_CLK_ECSPI2_CG 0x134 +#define IMX8MQ_CLK_ECSPI2_PRE_DIV 0x135 +#define IMX8MQ_CLK_ECSPI2_DIV 0x136 #define IMX8MQ_CLK_PCIE2_CTRL_SRC 0x17b #define IMX8MQ_CLK_PCIE2_CTRL_CG 0x17c #define IMX8MQ_CLK_PCIE2_CTRL_PRE_DIV 0x17d @@ -393,6 +401,13 @@ struct imxccm_mux imx7d_muxs[] = { #define IMX8MQ_CLK_PCIE2_AUX_CG 0x184 #define IMX8MQ_CLK_PCIE2_AUX_PRE_DIV 0x185 #define IMX8MQ_CLK_PCIE2_AUX_DIV 0x186 +#define IMX8MQ_CLK_ECSPI3_SRC 0x187 +#define IMX8MQ_CLK_ECSPI3_CG 0x188 +#define IMX8MQ_CLK_ECSPI3_PRE_DIV 0x189 +#define IMX8MQ_CLK_ECSPI3_DIV 0x18a +#define IMX8MQ_CLK_ECSPI1_ROOT 0x18d +#define IMX8MQ_CLK_ECSPI2_ROOT 0x18e +#define IMX8MQ_CLK_ECSPI3_ROOT 0x18f #define IMX8MQ_CLK_ENET1_ROOT 0x190 #define IMX8MQ_CLK_I2C1_ROOT 0x192 #define IMX8MQ_CLK_I2C2_ROOT 0x193 @@ -433,9 +448,15 @@ struct imxccm_gate imx8mq_gates[] = { [IMX8MQ_CLK_UART4_CG] = { 0xb080, 14, IMX8MQ_CLK_UART4_SRC }, [IMX8MQ_CLK_USB_CORE_REF_CG] = { 0xb100, 14, IMX8MQ_CLK_USB_CORE_REF_SRC }, [IMX8MQ_CLK_USB_PHY_REF_CG] = { 0xb180, 14, IMX8MQ_CLK_USB_PHY_REF_SRC }, + [IMX8MQ_CLK_ECSPI1_CG] = { 0xb280, 14, IMX8MQ_CLK_ECSPI1_SRC }, + [IMX8MQ_CLK_ECSPI2_CG] = { 0xb300, 14, IMX8MQ_CLK_ECSPI2_SRC }, [IMX8MQ_CLK_PCIE2_CTRL_CG] = { 0xc000, 14, IMX8MQ_CLK_PCIE2_CTRL_SRC }, [IMX8MQ_CLK_PCIE2_PHY_CG] = { 0xc080, 14, IMX8MQ_CLK_PCIE2_PHY_SRC }, [IMX8MQ_CLK_PCIE2_AUX_CG] = { 0xc100, 14, IMX8MQ_CLK_PCIE2_AUX_SRC }, + [IMX8MQ_CLK_ECSPI3_CG] = { 0xc180, 14, IMX8MQ_CLK_ECSPI3_SRC }, + [IMX8MQ_CLK_ECSPI1_ROOT] = { 0x4070, 0, IMX8MQ_CLK_ECSPI1_DIV }, + [IMX8MQ_CLK_ECSPI2_ROOT] = { 0x4080, 0, IMX8MQ_CLK_ECSPI2_DIV }, + [IMX8MQ_CLK_ECSPI3_ROOT] = { 0x4090, 0, IMX8MQ_CLK_ECSPI3_DIV }, [IMX8MQ_CLK_ENET1_ROOT] = { 0x40a0, 0, IMX8MQ_CLK_ENET_AXI_DIV }, [IMX8MQ_CLK_I2C1_ROOT] = { 0x4170, 0, IMX8MQ_CLK_I2C1_DIV }, [IMX8MQ_CLK_I2C2_ROOT] = { 0x4180, 0, IMX8MQ_CLK_I2C2_DIV }, @@ -497,12 +518,18 @@ struct imxccm_divider imx8mq_divs[] = { [IMX8MQ_CLK_USB_CORE_REF_DIV] = { 0xb100, 0, 0x3f, IMX8MQ_CLK_USB_CORE_REF_PRE_DIV }, [IMX8MQ_CLK_USB_PHY_REF_PRE_DIV] = { 0xb180, 16, 0x7, IMX8MQ_CLK_USB_PHY_REF_CG }, [IMX8MQ_CLK_USB_PHY_REF_DIV] = { 0xb180, 0, 0x3f, IMX8MQ_CLK_USB_PHY_REF_PRE_DIV }, + [IMX8MQ_CLK_ECSPI1_PRE_DIV] = { 0xb280, 16, 0x7, IMX8MQ_CLK_ECSPI1_CG }, + [IMX8MQ_CLK_ECSPI1_DIV] = { 0xb280, 0, 0x3f, IMX8MQ_CLK_ECSPI1_PRE_DIV }, + [IMX8MQ_CLK_ECSPI2_PRE_DIV] = { 0xb300, 16, 0x7, IMX8MQ_CLK_ECSPI2_CG }, + [IMX8MQ_CLK_ECSPI2_DIV] = { 0xb300, 0, 0x3f, IMX8MQ_CLK_ECSPI2_PRE_DIV }, [IMX8MQ_CLK_PCIE2_CTRL_PRE_DIV] = { 0xc000, 16, 0x7, IMX8MQ_CLK_PCIE2_CTRL_CG }, [IMX8MQ_CLK_PCIE2_CTRL_DIV] = { 0xc000, 0, 0x3f, IMX8MQ_CLK_PCIE2_CTRL_PRE_DIV }, [IMX8MQ_CLK_PCIE2_PHY_PRE_DIV] = { 0xc080, 16, 0x7, IMX8MQ_CLK_PCIE2_CTRL_CG }, [IMX8MQ_CLK_PCIE2_PHY_DIV] = { 0xc080, 0, 0x3f, IMX8MQ_CLK_PCIE2_CTRL_PRE_DIV }, [IMX8MQ_CLK_PCIE2_AUX_PRE_DIV] = { 0xc100, 16, 0x7, IMX8MQ_CLK_PCIE2_AUX_CG }, [IMX8MQ_CLK_PCIE2_AUX_DIV] = { 0xc100, 0, 0x3f, IMX8MQ_CLK_PCIE2_AUX_PRE_DIV }, + [IMX8MQ_CLK_ECSPI3_PRE_DIV] = { 0xc180, 16, 0x7, IMX8MQ_CLK_ECSPI3_CG }, + [IMX8MQ_CLK_ECSPI3_DIV] = { 0xc180, 0, 0x3f, IMX8MQ_CLK_ECSPI3_PRE_DIV }, }; struct imxccm_mux imx8mq_muxs[] = { @@ -527,7 +554,10 @@ struct imxccm_mux imx8mq_muxs[] = { [IMX8MQ_CLK_UART4_SRC] = { 0xb080, 24, 0x7 }, [IMX8MQ_CLK_USB_CORE_REF_SRC] = { 0xb100, 24, 0x7 }, [IMX8MQ_CLK_USB_PHY_REF_SRC] = { 0xb180, 24, 0x7 }, + [IMX8MQ_CLK_ECSPI1_SRC] = { 0xb280, 24, 0x7 }, + [IMX8MQ_CLK_ECSPI2_SRC] = { 0xb300, 24, 0x7 }, [IMX8MQ_CLK_PCIE2_CTRL_SRC] = { 0xc000, 24, 0x7 }, [IMX8MQ_CLK_PCIE2_PHY_SRC] = { 0xc080, 24, 0x7 }, [IMX8MQ_CLK_PCIE2_AUX_SRC] = { 0xc100, 24, 0x7 }, + [IMX8MQ_CLK_ECSPI3_SRC] = { 0xc180, 24, 0x7 }, }; -- 2.20.1