From 8e8fc6d26dd88a2a42b6a2e99d42b8960de88b6d Mon Sep 17 00:00:00 2001 From: jsg Date: Tue, 13 Aug 2024 02:19:41 +0000 Subject: [PATCH] drm/i915: Fix possible int overflow in skl_ddi_calculate_wrpll() From Nikita Zhandarovich 6c0473c9ac502df8d580c15f20188efe708e8394 in linux-6.6.y/6.6.45 5b511572660190db1dc8ba412efd0be0d3781ab6 in mainline linux --- sys/dev/pci/drm/i915/display/intel_dpll_mgr.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/sys/dev/pci/drm/i915/display/intel_dpll_mgr.c b/sys/dev/pci/drm/i915/display/intel_dpll_mgr.c index bd650a162ba..77a33ec6365 100644 --- a/sys/dev/pci/drm/i915/display/intel_dpll_mgr.c +++ b/sys/dev/pci/drm/i915/display/intel_dpll_mgr.c @@ -1556,7 +1556,7 @@ static void skl_wrpll_params_populate(struct skl_wrpll_params *params, } static int -skl_ddi_calculate_wrpll(int clock /* in Hz */, +skl_ddi_calculate_wrpll(int clock, int ref_clock, struct skl_wrpll_params *wrpll_params) { @@ -1581,7 +1581,7 @@ skl_ddi_calculate_wrpll(int clock /* in Hz */, }; unsigned int dco, d, i; unsigned int p0, p1, p2; - u64 afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */ + u64 afe_clock = (u64)clock * 1000 * 5; /* AFE Clock is 5x Pixel clock, in Hz */ for (d = 0; d < ARRAY_SIZE(dividers); d++) { for (dco = 0; dco < ARRAY_SIZE(dco_central_freq); dco++) { @@ -1713,7 +1713,7 @@ static int skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state) ctrl1 |= DPLL_CTRL1_HDMI_MODE(0); - ret = skl_ddi_calculate_wrpll(crtc_state->port_clock * 1000, + ret = skl_ddi_calculate_wrpll(crtc_state->port_clock, i915->display.dpll.ref_clks.nssc, &wrpll_params); if (ret) return ret; -- 2.20.1