From 8db7132f631c1d8e83cb39292fe23261dc381959 Mon Sep 17 00:00:00 2001 From: patrick Date: Sun, 26 Dec 2021 20:50:17 +0000 Subject: [PATCH] Add information about TCM rambase and how to check the SR capability for a few more chips. --- sys/dev/ic/bwfm.c | 38 +++++++++++++++++++++++++++++++------- sys/dev/ic/bwfmreg.h | 3 ++- sys/dev/ic/bwfmvar.h | 10 +++++++++- 3 files changed, 42 insertions(+), 9 deletions(-) diff --git a/sys/dev/ic/bwfm.c b/sys/dev/ic/bwfm.c index 4c473b53d4c..e9ccba46005 100644 --- a/sys/dev/ic/bwfm.c +++ b/sys/dev/ic/bwfm.c @@ -1,4 +1,4 @@ -/* $OpenBSD: bwfm.c,v 1.92 2021/12/22 19:37:33 tobhe Exp $ */ +/* $OpenBSD: bwfm.c,v 1.93 2021/12/26 20:50:17 patrick Exp $ */ /* * Copyright (c) 2010-2016 Broadcom Corporation * Copyright (c) 2016,2017 Patrick Wildt @@ -1407,6 +1407,19 @@ bwfm_chip_sr_capable(struct bwfm_softc *sc) reg = sc->sc_buscore_ops->bc_read(sc, core->co_base + BWFM_CHIP_REG_SR_CONTROL1); return reg != 0; + case CY_CC_4373_CHIP_ID: + core = bwfm_chip_get_core(sc, BWFM_AGENT_CORE_CHIPCOMMON); + reg = sc->sc_buscore_ops->bc_read(sc, core->co_base + + BWFM_CHIP_REG_SR_CONTROL0); + return (reg & BWFM_CHIP_REG_SR_CONTROL0_ENABLE) != 0; + case BRCM_CC_4359_CHIP_ID: + case CY_CC_43752_CHIP_ID: + case CY_CC_43012_CHIP_ID: + core = bwfm_chip_get_pmu(sc); + reg = sc->sc_buscore_ops->bc_read(sc, core->co_base + + BWFM_CHIP_REG_RETENTION_CTL); + return (reg & (BWFM_CHIP_REG_RETENTION_CTL_MACPHY_DIS | + BWFM_CHIP_REG_RETENTION_CTL_LOGIC_DIS)) == 0; case BRCM_CC_4378_CHIP_ID: return 0; default: @@ -1553,24 +1566,35 @@ bwfm_chip_tcm_rambase(struct bwfm_softc *sc) case BRCM_CC_4371_CHIP_ID: sc->sc_chip.ch_rambase = 0x180000; break; - case BRCM_CC_4359_CHIP_ID: - if (sc->sc_chip.ch_chiprev < 9) - sc->sc_chip.ch_rambase = 0x180000; - else - sc->sc_chip.ch_rambase = 0x160000; - break; case BRCM_CC_43465_CHIP_ID: case BRCM_CC_43525_CHIP_ID: case BRCM_CC_4365_CHIP_ID: case BRCM_CC_4366_CHIP_ID: + case BRCM_CC_43664_CHIP_ID: + case BRCM_CC_43666_CHIP_ID: sc->sc_chip.ch_rambase = 0x200000; break; + case BRCM_CC_4359_CHIP_ID: + if (sc->sc_chip.ch_chiprev < 9) + sc->sc_chip.ch_rambase = 0x180000; + else + sc->sc_chip.ch_rambase = 0x160000; + break; + case BRCM_CC_4355_CHIP_ID: + case BRCM_CC_4364_CHIP_ID: case CY_CC_4373_CHIP_ID: sc->sc_chip.ch_rambase = 0x160000; break; + case BRCM_CC_4377_CHIP_ID: + case CY_CC_43752_CHIP_ID: + sc->sc_chip.ch_rambase = 0x170000; + break; case BRCM_CC_4378_CHIP_ID: sc->sc_chip.ch_rambase = 0x352000; break; + case BRCM_CC_4387_CHIP_ID: + sc->sc_chip.ch_rambase = 0x740000; + break; default: printf("%s: unknown chip: %d\n", DEVNAME(sc), sc->sc_chip.ch_chip); diff --git a/sys/dev/ic/bwfmreg.h b/sys/dev/ic/bwfmreg.h index 997caf5c3a5..4bfbc298ee6 100644 --- a/sys/dev/ic/bwfmreg.h +++ b/sys/dev/ic/bwfmreg.h @@ -1,4 +1,4 @@ -/* $OpenBSD: bwfmreg.h,v 1.21 2021/02/26 12:33:59 patrick Exp $ */ +/* $OpenBSD: bwfmreg.h,v 1.22 2021/12/26 20:50:17 patrick Exp $ */ /* * Copyright (c) 2010-2016 Broadcom Corporation * Copyright (c) 2016,2017 Patrick Wildt @@ -34,6 +34,7 @@ #define BWFM_CHIP_REG_EROMPTR 0x000000FC #define BWFM_CHIP_REG_SR_CAPABILITY 0x00000500 #define BWFM_CHIP_REG_SR_CONTROL0 0x00000504 +#define BWFM_CHIP_REG_SR_CONTROL0_ENABLE (1 << 0) #define BWFM_CHIP_REG_SR_CONTROL1 0x00000508 #define BWFM_CHIP_REG_PMUCONTROL 0x00000600 #define BWFM_CHIP_REG_PMUCONTROL_RES_MASK 0x00006000 diff --git a/sys/dev/ic/bwfmvar.h b/sys/dev/ic/bwfmvar.h index f3304f71560..5997138a1f9 100644 --- a/sys/dev/ic/bwfmvar.h +++ b/sys/dev/ic/bwfmvar.h @@ -1,4 +1,4 @@ -/* $OpenBSD: bwfmvar.h,v 1.26 2021/12/20 19:24:32 patrick Exp $ */ +/* $OpenBSD: bwfmvar.h,v 1.27 2021/12/26 20:50:17 patrick Exp $ */ /* * Copyright (c) 2010-2016 Broadcom Corporation * Copyright (c) 2016,2017 Patrick Wildt @@ -37,6 +37,7 @@ #define BRCM_CC_4350_CHIP_ID 0x4350 #define BRCM_CC_43525_CHIP_ID 43525 #define BRCM_CC_4354_CHIP_ID 0x4354 +#define BRCM_CC_4355_CHIP_ID 0x4355 #define BRCM_CC_4356_CHIP_ID 0x4356 #define BRCM_CC_43566_CHIP_ID 43566 #define BRCM_CC_43567_CHIP_ID 43567 @@ -45,11 +46,18 @@ #define BRCM_CC_4358_CHIP_ID 0x4358 #define BRCM_CC_4359_CHIP_ID 0x4359 #define BRCM_CC_43602_CHIP_ID 43602 +#define BRCM_CC_4364_CHIP_ID 0x4364 #define BRCM_CC_4365_CHIP_ID 0x4365 #define BRCM_CC_4366_CHIP_ID 0x4366 +#define BRCM_CC_43664_CHIP_ID 43664 +#define BRCM_CC_43666_CHIP_ID 43666 #define BRCM_CC_4371_CHIP_ID 0x4371 +#define BRCM_CC_4377_CHIP_ID 0x4377 #define BRCM_CC_4378_CHIP_ID 0x4378 +#define BRCM_CC_4387_CHIP_ID 0x4387 #define CY_CC_4373_CHIP_ID 0x4373 +#define CY_CC_43012_CHIP_ID 43012 +#define CY_CC_43752_CHIP_ID 43752 /* Defaults */ #define BWFM_DEFAULT_SCAN_CHANNEL_TIME 40 -- 2.20.1