From 8b31f2a3f55c8d09564674ca1e639faa55ce65be Mon Sep 17 00:00:00 2001 From: visa Date: Tue, 18 Jan 2022 07:53:39 +0000 Subject: [PATCH] Add cdsdhc(4), a driver for the Cadence SD/SDIO/eMMC host controller. Tested on a PolarFire SoC. --- share/man/man4/Makefile | 4 +- share/man/man4/cdsdhc.4 | 40 ++++++++ sys/arch/riscv64/conf/GENERIC | 4 +- sys/arch/riscv64/conf/RAMDISK | 4 +- sys/dev/fdt/cdsdhc.c | 168 ++++++++++++++++++++++++++++++++++ sys/dev/fdt/files.fdt | 6 +- 6 files changed, 221 insertions(+), 5 deletions(-) create mode 100644 share/man/man4/cdsdhc.4 create mode 100644 sys/dev/fdt/cdsdhc.c diff --git a/share/man/man4/Makefile b/share/man/man4/Makefile index 76ecf61b10f..9c2d00569c3 100644 --- a/share/man/man4/Makefile +++ b/share/man/man4/Makefile @@ -1,4 +1,4 @@ -# $OpenBSD: Makefile,v 1.816 2022/01/10 04:59:19 jsg Exp $ +# $OpenBSD: Makefile,v 1.817 2022/01/18 07:53:39 visa Exp $ MAN= aac.4 abcrtc.4 abl.4 ac97.4 acphy.4 acrtc.4 \ acpi.4 acpiac.4 acpials.4 acpiasus.4 acpibat.4 \ @@ -24,7 +24,7 @@ MAN= aac.4 abcrtc.4 abl.4 ac97.4 acphy.4 acrtc.4 \ berkwdt.4 bge.4 bgw.4 bio.4 bpe.4 bktr.4 bmtphy.4 bnx.4 bnxt.4 \ boca.4 bpf.4 brgphy.4 bridge.4 brswphy.4 bse.4 bwfm.4 bwi.4 bytgpio.4 \ cac.4 cad.4 cas.4 cardbus.4 carp.4 ccp.4 ccpmic.4 cd.4 cdce.4 \ - cduart.4 cfxga.4 \ + cdsdhc.4 cduart.4 cfxga.4 \ ch.4 chvgpio.4 ciphy.4 ciss.4 clcs.4 clct.4 cmpci.4 \ com.4 cue.4 cwfg.4 cy.4 cz.4 \ dapmic.4 \ diff --git a/share/man/man4/cdsdhc.4 b/share/man/man4/cdsdhc.4 new file mode 100644 index 00000000000..9203eff4c73 --- /dev/null +++ b/share/man/man4/cdsdhc.4 @@ -0,0 +1,40 @@ +.\" $OpenBSD: cdsdhc.4,v 1.1 2022/01/18 07:53:39 visa Exp $ +.\" +.\" Copyright (c) 2022 Visa Hankala +.\" +.\" Permission to use, copy, modify, and distribute this software for any +.\" purpose with or without fee is hereby granted, provided that the above +.\" copyright notice and this permission notice appear in all copies. +.\" +.\" THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +.\" WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +.\" MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +.\" ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +.\" WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +.\" ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +.\" OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +.\" +.Dd $Mdocdate: January 18 2022 $ +.Dt CDSDHC 4 +.Os +.Sh NAME +.Nm cdsdhc +.Nd Cadence SD/SDIO/eMMC host controller +.Sh SYNOPSIS +.Cd "cdsdhc* at fdt?" +.Cd "sdmmc* at cdsdhc?" +.Sh DESCRIPTION +The +.Nm +driver provides support for the Cadence SD/SDIO/eMMC host controller, +which provides an interface to the +.Xr sdmmc 4 +bus. +.Sh SEE ALSO +.Xr intro 4 , +.Xr sdmmc 4 +.Sh HISTORY +The +.Nm +driver first appeared in +.Ox 7.1 . diff --git a/sys/arch/riscv64/conf/GENERIC b/sys/arch/riscv64/conf/GENERIC index 3024748578e..31014e90122 100644 --- a/sys/arch/riscv64/conf/GENERIC +++ b/sys/arch/riscv64/conf/GENERIC @@ -1,4 +1,4 @@ -# $OpenBSD: GENERIC,v 1.32 2022/01/05 03:32:44 visa Exp $ +# $OpenBSD: GENERIC,v 1.33 2022/01/18 07:53:39 visa Exp $ # # For further information on compiling OpenBSD kernels, see the config(8) # man page. @@ -45,6 +45,8 @@ intc0 at cpu0 com* at fdt? # PolarFire SoCs +cdsdhc* at fdt? +sdmmc* at cdsdhc? mpfclock* at fdt? early 1 # SiFive SoCs diff --git a/sys/arch/riscv64/conf/RAMDISK b/sys/arch/riscv64/conf/RAMDISK index 74993f13161..74397a579a8 100644 --- a/sys/arch/riscv64/conf/RAMDISK +++ b/sys/arch/riscv64/conf/RAMDISK @@ -1,4 +1,4 @@ -# $OpenBSD: RAMDISK,v 1.28 2022/01/05 03:32:44 visa Exp $ +# $OpenBSD: RAMDISK,v 1.29 2022/01/18 07:53:39 visa Exp $ machine riscv64 maxusers 4 @@ -36,6 +36,8 @@ intc0 at cpu0 com* at fdt? # PolarFire SoCs +cdsdhc* at fdt? +sdmmc* at cdsdhc? mpfclock* at fdt? early 1 # SiFive SoCs diff --git a/sys/dev/fdt/cdsdhc.c b/sys/dev/fdt/cdsdhc.c new file mode 100644 index 00000000000..df3b760b43b --- /dev/null +++ b/sys/dev/fdt/cdsdhc.c @@ -0,0 +1,168 @@ +/* $OpenBSD: cdsdhc.c,v 1.1 2022/01/18 07:53:39 visa Exp $ */ + +/* + * Copyright (c) 2022 Visa Hankala + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +/* + * Driver glue for Cadence SD/SDIO/eMMC host controller. + */ + +#include +#include +#include +#include + +#include +#include + +#include +#include +#include + +#include +#include + +/* Host Register Set */ +#define HRS06 0x0018 +#define HRS06_ETR (0x1 << 15) +#define HRS06_ETV_MASK (0x3f << 8) +#define HRS06_ETV_SHIFT 8 +#define HRS06_EMM_MASK (0x7 << 0) +#define HRS06_EMM_SD (0x0 << 0) +#define HRS06_EMM_MMC_SDR (0x2 << 0) +#define HRS06_EMM_MMC_DDR (0x3 << 0) +#define HRS06_EMM_MMC_HS200 (0x4 << 0) +#define HRS06_EMM_MMC_HS400 (0x5 << 0) +#define HRS06_EMM_MMC_HS400_ENH (0x6 << 0) +#define HRS31 0x007c +#define HRS31_HOSTCTLVER(x) (((x) >> 16) & 0xfff) +#define HRS31_HOSTFIXVER(x) ((x) & 0xff) + +/* Slot Register Set */ +#define SRS_OFFSET 0x200 +#define SRS_SIZE 0x100 + +struct cdsdhc_softc { + struct sdhc_softc sc_sdhc; + bus_space_tag_t sc_iot; + bus_space_handle_t sc_ioh; + bus_space_handle_t sc_srs_ioh; + void *sc_ih; + + struct sdhc_host *sc_host; +}; + +#define HREAD4(sc, reg) \ + (bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))) +#define HWRITE4(sc, reg, val) \ + bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) + +int cdsdhc_match(struct device *, void *, void*); +void cdsdhc_attach(struct device *, struct device *, void *); +void cdsdhc_bus_clock_pre(struct sdhc_softc *, int, int); + +const struct cfattach cdsdhc_ca = { + sizeof(struct cdsdhc_softc), cdsdhc_match, cdsdhc_attach +}; + +struct cfdriver cdsdhc_cd = { + NULL, "cdsdhc", DV_DULL +}; + +int +cdsdhc_match(struct device *parent, void *match, void *aux) +{ + struct fdt_attach_args *faa = aux; + + if (faa->fa_nreg < 1) + return 0; + return OF_is_compatible(faa->fa_node, "cdns,sd4hc"); +} + +void +cdsdhc_attach(struct device *parent, struct device *self, void *aux) +{ + struct fdt_attach_args *faa = aux; + struct cdsdhc_softc *sc = (struct cdsdhc_softc *)self; + uint32_t caps = 0; + uint32_t ver; + + sc->sc_iot = faa->fa_iot; + + if (bus_space_map(sc->sc_iot, faa->fa_reg[0].addr, faa->fa_reg[0].size, + 0, &sc->sc_ioh) != 0) { + printf(": can't map registers\n"); + return; + } + + if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, SRS_OFFSET, SRS_SIZE, + &sc->sc_srs_ioh) != 0) { + printf(": can't map SRS subregion\n"); + goto unmap; + } + + clock_enable_all(faa->fa_node); + + sc->sc_ih = fdt_intr_establish(faa->fa_node, IPL_BIO, + sdhc_intr, sc, sc->sc_sdhc.sc_dev.dv_xname); + if (sc->sc_ih == NULL) { + printf(": can't establish interrupt\n"); + goto disable; + } + + ver = HREAD4(sc, HRS31); + printf(": rev 0x%x/0x%x\n", HRS31_HOSTCTLVER(ver), + HRS31_HOSTFIXVER(ver)); + + sc->sc_sdhc.sc_host = &sc->sc_host; + sc->sc_sdhc.sc_dmat = faa->fa_dmat; + sc->sc_sdhc.sc_bus_clock_pre = cdsdhc_bus_clock_pre; + sdhc_host_found(&sc->sc_sdhc, sc->sc_iot, sc->sc_srs_ioh, SRS_SIZE, + 1, caps); + return; + +disable: + clock_disable_all(faa->fa_node); +unmap: + bus_space_unmap(sc->sc_iot, sc->sc_ioh, faa->fa_reg[0].size); +} + +void +cdsdhc_bus_clock_pre(struct sdhc_softc *sc_sdhc, int freq, int timing) +{ + struct cdsdhc_softc *sc = (struct cdsdhc_softc *)sc_sdhc; + uint32_t mode, val; + + switch (timing) { + case SDMMC_TIMING_HIGHSPEED: + mode = HRS06_EMM_MMC_SDR; + break; + case SDMMC_TIMING_MMC_DDR52: + mode = HRS06_EMM_MMC_DDR; + break; + case SDMMC_TIMING_MMC_HS200: + mode = HRS06_EMM_MMC_HS200; + break; + default: + mode = HRS06_EMM_SD; + break; + } + + val = HREAD4(sc, HRS06); + val &= ~HRS06_EMM_MASK; + val |= mode; + HWRITE4(sc, HRS06, val); +} diff --git a/sys/dev/fdt/files.fdt b/sys/dev/fdt/files.fdt index cfc14e7b7ec..569db67c783 100644 --- a/sys/dev/fdt/files.fdt +++ b/sys/dev/fdt/files.fdt @@ -1,4 +1,4 @@ -# $OpenBSD: files.fdt,v 1.160 2021/11/21 11:02:21 kettenis Exp $ +# $OpenBSD: files.fdt,v 1.161 2022/01/18 07:53:39 visa Exp $ # # Config file and device description for machine-independent FDT code. # Included by ports that need it. @@ -289,6 +289,10 @@ device cad: ether, ifnet, mii, ifmedia attach cad at fdt file dev/fdt/if_cad.c cad +device cdsdhc: sdmmcbus, sdhc +attach cdsdhc at fdt +file dev/fdt/cdsdhc.c cdsdhc + device cduart attach cduart at fdt file dev/fdt/cduart.c cduart -- 2.20.1