From 8a3a1b1f26ea0edae5a4c15365e72bba05210047 Mon Sep 17 00:00:00 2001 From: kevlo Date: Sat, 2 Apr 2022 12:22:56 +0000 Subject: [PATCH] Add preliminary support for RTL8156B and bug fixes for RTL8153/RTL8156. ok stsp@ Tested: RTL8152 (0x4c10): jmatthew, Marcus Merighi RTL8153 (0x5c10): Yifei Zhan RTL8153 (0x5c20): James Jerkins, Paul de Weerd, stsp RTL8153 (0x5c30): gerhard, sthen RTL8153B (0x6010): Paul de Weerd --- sys/dev/usb/if_ure.c | 336 ++++++++++++++++++++++++++-------------- sys/dev/usb/if_urereg.h | 93 ++++++++++- 2 files changed, 314 insertions(+), 115 deletions(-) diff --git a/sys/dev/usb/if_ure.c b/sys/dev/usb/if_ure.c index 31e92826594..4946163ba89 100644 --- a/sys/dev/usb/if_ure.c +++ b/sys/dev/usb/if_ure.c @@ -1,4 +1,4 @@ -/* $OpenBSD: if_ure.c,v 1.28 2021/08/20 04:54:10 kevlo Exp $ */ +/* $OpenBSD: if_ure.c,v 1.29 2022/04/02 12:22:56 kevlo Exp $ */ /*- * Copyright (c) 2015, 2016, 2019 Kevin Lo * Copyright (c) 2020 Jonathon Fletcher @@ -197,7 +197,8 @@ void ure_rtl8153_init(struct ure_softc *); void ure_rtl8153b_init(struct ure_softc *); void ure_rtl8152_nic_reset(struct ure_softc *); void ure_rtl8153_nic_reset(struct ure_softc *); -void ure_rtl8153_phy_status(struct ure_softc *, int); +uint16_t ure_rtl8153_phy_status(struct ure_softc *, int); +void ure_wait_for_flash(struct ure_softc *); void ure_reset_bmu(struct ure_softc *); void ure_disable_teredo(struct ure_softc *); @@ -458,14 +459,19 @@ ure_ifmedia_init(struct ifnet *ifp) ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_NORAML); if (!(sc->ure_flags & URE_FLAG_8152)) { + if (sc->ure_flags & URE_FLAG_8156B) + URE_CLRBIT_2(sc, URE_USB_RX_AGGR_NUM, URE_MCU_TYPE_USB, + URE_RX_AGGR_NUM_MASK); + reg = sc->ure_rxbufsz - URE_FRAMELEN(ifp->if_mtu) - sizeof(struct ure_rxpkt) - URE_RX_BUF_ALIGN; - if (sc->ure_flags & (URE_FLAG_8153B | URE_FLAG_8156)) { + if (sc->ure_flags & (URE_FLAG_8153B | URE_FLAG_8156 | + URE_FLAG_8156B)) { ure_write_2(sc, URE_USB_RX_EARLY_SIZE, URE_MCU_TYPE_USB, reg / 8); ure_write_2(sc, URE_USB_RX_EARLY_AGG, URE_MCU_TYPE_USB, - (sc->ure_flags & URE_FLAG_8153B) ? 16 : 80); + (sc->ure_flags & URE_FLAG_8153B) ? 158 : 80); ure_write_2(sc, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB, 1875); } else { @@ -485,6 +491,15 @@ ure_ifmedia_init(struct ifnet *ifp) ure_write_2(sc, URE_USB_RX_EARLY_AGG, URE_MCU_TYPE_USB, reg); } + + if ((sc->ure_chip & URE_CHIP_VER_6010) || + (sc->ure_flags & URE_FLAG_8156B)) { + URE_CLRBIT_2(sc, URE_USB_FW_TASK, URE_MCU_TYPE_USB, + URE_FC_PATCH_TASK); + usbd_delay_ms(sc->ure_udev, 1); + URE_SETBIT_2(sc, URE_USB_FW_TASK, URE_MCU_TYPE_USB, + URE_FC_PATCH_TASK); + } } /* Reset the packet filter. */ @@ -494,7 +509,7 @@ ure_ifmedia_init(struct ifnet *ifp) /* Enable transmit and receive. */ URE_SETBIT_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RE | URE_CR_TE); - if (sc->ure_flags & (URE_FLAG_8153B | URE_FLAG_8156)) { + if (sc->ure_flags & (URE_FLAG_8153B | URE_FLAG_8156 | URE_FLAG_8156B)) { ure_write_1(sc, URE_USB_UPT_RXDMA_OWN, URE_MCU_TYPE_USB, URE_OWN_UPDATE | URE_OWN_CLEAR); } @@ -510,7 +525,7 @@ ure_ifmedia_upd(struct ifnet *ifp) struct ifmedia *ifm = &sc->ure_ifmedia; int anar, gig, err, reg; - if (sc->ure_flags & URE_FLAG_8156) { + if (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) return (EINVAL); @@ -579,7 +594,7 @@ ure_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) struct mii_data *mii = &sc->ure_mii; uint16_t status = 0; - if (sc->ure_flags & URE_FLAG_8156) { + if (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { ifmr->ifm_status = IFM_AVALID; if (ure_get_link_status(sc)) { ifmr->ifm_status |= IFM_ACTIVE; @@ -711,12 +726,12 @@ ure_rxvlan(struct ure_softc *sc) struct ifnet *ifp = &sc->ure_ac.ac_if; uint16_t reg; - if (sc->ure_flags & URE_FLAG_8156) { - reg = ure_read_2(sc, 0xc012, URE_MCU_TYPE_PLA); - reg &= ~0x00c0; + if (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { + reg = ure_read_2(sc, URE_PLA_RCR1, URE_MCU_TYPE_PLA); + reg &= ~(URE_INNER_VLAN | URE_OUTER_VLAN); if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) - reg |= 0x00c0; - ure_write_2(sc, 0xc012, URE_MCU_TYPE_PLA, reg); + reg |= (URE_INNER_VLAN | URE_OUTER_VLAN); + ure_write_2(sc, URE_PLA_RCR1, URE_MCU_TYPE_PLA, reg); } else { reg = ure_read_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA); reg &= ~URE_CPCR_RX_VLAN; @@ -731,16 +746,30 @@ ure_reset(struct ure_softc *sc) { int i; - ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RST); + if (sc->ure_flags & URE_FLAG_8156) { + URE_CLRBIT_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_TE); + URE_CLRBIT_2(sc, URE_USB_BMU_RESET, URE_MCU_TYPE_USB, + BMU_RESET_EP_IN); + URE_SETBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, + URE_CDC_ECM_EN); + URE_CLRBIT_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RE); + URE_SETBIT_2(sc, URE_USB_BMU_RESET, URE_MCU_TYPE_USB, + BMU_RESET_EP_IN); + URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, + URE_CDC_ECM_EN); + } else { + ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RST); - for (i = 0; i < URE_TIMEOUT; i++) { - if (!(ure_read_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA) & - URE_CR_RST)) - break; - DELAY(100); + for (i = 0; i < URE_TIMEOUT; i++) { + if (!(ure_read_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA) & + URE_CR_RST)) + break; + DELAY(100); + } + if (i == URE_TIMEOUT) + printf("%s: reset never completed\n", + sc->ure_dev.dv_xname); } - if (i == URE_TIMEOUT) - printf("%s: reset never completed\n", sc->ure_dev.dv_xname); } void @@ -1120,7 +1149,7 @@ ure_rtl8153_init(struct ure_softc *sc) URE_CKADSEL_L | URE_ADC_EN | URE_EN_EMI_L); } - ure_rtl8153_phy_status(sc, 1); + ure_rtl8153_phy_status(sc, URE_PHY_STAT_LAN_ON); URE_CLRBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE); @@ -1193,14 +1222,23 @@ ure_rtl8153b_init(struct ure_softc *sc) uint16_t reg; int i; - if (sc->ure_flags & URE_FLAG_8156) { - URE_CLRBIT_1(sc, 0xd26b, URE_MCU_TYPE_USB, 0x01); - ure_write_2(sc, 0xd32a, URE_MCU_TYPE_USB, 0); - URE_SETBIT_2(sc, 0xcfee, URE_MCU_TYPE_USB, 0x0020); + if (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { + URE_CLRBIT_1(sc, URE_USB_ECM_OP, URE_MCU_TYPE_USB, + URE_EN_ALL_SPEED); + ure_write_2(sc, URE_USB_SPEED_OPTION, URE_MCU_TYPE_USB, 0); + URE_SETBIT_2(sc, URE_USB_ECM_OPTION, URE_MCU_TYPE_USB, + URE_BYPASS_MAC_RESET); + + if (sc->ure_flags & URE_FLAG_8156B) + URE_SETBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, + URE_RX_DETECT8); } URE_CLRBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, LPM_U1U2_EN); + if (sc->ure_flags & URE_FLAG_8156B) + ure_wait_for_flash(sc); + for (i = 0; i < 500; i++) { if (ure_read_2(sc, URE_PLA_BOOT_CTRL, URE_MCU_TYPE_PLA) & URE_AUTOLOAD_DONE) @@ -1212,28 +1250,25 @@ ure_rtl8153b_init(struct ure_softc *sc) sc->ure_dev.dv_xname); ure_rtl8153_phy_status(sc, 0); - ure_rtl8153_phy_status(sc, 1); + ure_rtl8153_phy_status(sc, URE_PHY_STAT_LAN_ON); URE_CLRBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE); /* MSC timer, 32760 ms. */ - ure_write_2(sc, URE_USB_MSC_TIMER, URE_MCU_TYPE_USB, 0x0fff); + ure_write_2(sc, URE_USB_MSC_TIMER, URE_MCU_TYPE_USB, 4095); - /* U1/U2/L1 idle timer, 500 us. */ - ure_write_2(sc, URE_USB_U1U2_TIMER, URE_MCU_TYPE_USB, 500); + if (!(sc->ure_flags & URE_FLAG_8153B)) { + /* U1/U2/L1 idle timer, 500 us. */ + ure_write_2(sc, URE_USB_U1U2_TIMER, URE_MCU_TYPE_USB, 500); + } URE_CLRBIT_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, URE_PWR_EN); URE_CLRBIT_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB, URE_PCUT_STATUS); URE_CLRBIT_1(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, URE_UPS_EN | URE_USP_PREWAKE); - URE_CLRBIT_1(sc, 0xcfff, URE_MCU_TYPE_USB, 0x01); - - if (!(sc->ure_flags & URE_FLAG_8156)) { - URE_CLRBIT_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB, - URE_PCUT_STATUS); - ure_rtl8153_phy_status(sc, 0); - } + URE_CLRBIT_1(sc, URE_USB_MISC_2, URE_MCU_TYPE_USB, + URE_UPS_FORCE_PWR_DOWN); URE_CLRBIT_1(sc, URE_PLA_INDICATE_FALG, URE_MCU_TYPE_PLA, URE_UPCOMING_RUNTIME_D3); @@ -1246,27 +1281,62 @@ ure_rtl8153b_init(struct ure_softc *sc) URE_CLRBIT_2(sc, URE_PLA_CONFIG34, URE_MCU_TYPE_PLA, URE_LINK_OFF_WAKE_EN); ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_NORAML); - - URE_SETBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, LPM_U1U2_EN); + if (sc->ure_flags & URE_FLAG_8153B) { + reg = ure_read_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_PLA); + if (ure_read_2(sc, URE_PLA_PHYSTATUS, URE_MCU_TYPE_PLA) & + URE_PHYSTATUS_LINK) + reg |= URE_CUR_LINK_OK; + else + reg &= ~URE_CUR_LINK_OK; + ure_write_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_PLA, + reg | URE_POLL_LINK_CHG); + } + + if (sc->ure_udev->speed == USB_SPEED_SUPER) { + URE_SETBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, + LPM_U1U2_EN); + } + + if (sc->ure_flags & URE_FLAG_8156B) { + URE_CLRBIT_2(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, URE_SLOT_EN); + URE_SETBIT_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA, + URE_FLOW_CTRL_EN); + + /* Enable fc timer and set timer to 600 ms. */ + ure_write_2(sc, URE_USB_FC_TIMER, URE_MCU_TYPE_USB, + URE_CTRL_TIMER_EN | 75); + + reg = ure_read_2(sc, URE_USB_FW_CTRL, URE_MCU_TYPE_USB); + if (!(ure_read_2(sc, URE_PLA_POL_GPIO_CTRL, URE_MCU_TYPE_PLA) & + URE_DACK_DET_EN)) + reg |= URE_FLOW_CTRL_PATCH_2; + reg &= ~URE_AUTO_SPEEDUP; + ure_write_2(sc, URE_USB_FW_CTRL, URE_MCU_TYPE_USB, reg); + + URE_SETBIT_2(sc, URE_USB_FW_TASK, URE_MCU_TYPE_USB, + URE_FC_PATCH_TASK); + } + /* MAC clock speed down. */ - if (sc->ure_flags & URE_FLAG_8156) { + if (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { ure_write_2(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, 0x0403); - reg = ure_read_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA) & - ~0xff; + reg = ure_read_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA); + reg &= ~URE_EEE_SPDWN_RATIO_MASK; reg |= URE_MAC_CLK_SPDWN_EN | 0x0003; ure_write_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA, reg); URE_CLRBIT_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, - 0x4000); + URE_PLA_MCU_SPDWN_EN); reg = ure_read_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_PLA); - if (ure_get_link_status(sc)) - reg |= 0x8000; + if (ure_read_2(sc, URE_PLA_PHYSTATUS, URE_MCU_TYPE_PLA) & + URE_PHYSTATUS_LINK) + reg |= URE_CUR_LINK_OK; else - reg &= ~0x8000; - reg |= 0x0001; - ure_write_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_PLA, reg); + reg &= ~URE_CUR_LINK_OK; + ure_write_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_PLA, + reg | URE_POLL_LINK_CHG); } else URE_SETBIT_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA, URE_MAC_CLK_SPDWN_EN); @@ -1276,7 +1346,8 @@ ure_rtl8153b_init(struct ure_softc *sc) URE_RX_AGG_DISABLE | URE_RX_ZERO_EN); if (sc->ure_flags & URE_FLAG_8156) - URE_SETBIT_1(sc, 0xcfd9, URE_MCU_TYPE_USB, 0x04); + URE_SETBIT_1(sc, URE_USB_BMU_CONFIG, URE_MCU_TYPE_USB, + URE_ACT_ODMA); URE_SETBIT_2(sc, URE_PLA_RSTTALLY, URE_MCU_TYPE_PLA, URE_TALLY_RESET); } @@ -1364,7 +1435,7 @@ ure_rtl8153_nic_reset(struct ure_softc *sc) uint8_t u1u2[8] = { 0 }; int i; - if (sc->ure_flags & (URE_FLAG_8153B | URE_FLAG_8156)) { + if (sc->ure_flags & (URE_FLAG_8153B | URE_FLAG_8156 | URE_FLAG_8156B)) { URE_CLRBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, LPM_U1U2_EN); } else { @@ -1382,33 +1453,19 @@ ure_rtl8153_nic_reset(struct ure_softc *sc) if (ure_read_2(sc, 0xe000, URE_MCU_TYPE_PLA) & 0x0100) break; } - if (sc->ure_flags & URE_FLAG_8153B) { - URE_CLRBIT_4(sc, URE_USB_UPS_FLAGS, URE_MCU_TYPE_USB, - URE_UPS_FLAGS_EN_ALDPS); - } - if (!(sc->ure_flags & URE_FLAG_8156)) { - ure_write_2(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, 0); - ure_write_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA, 0); - ure_write_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, 0); - ure_write_2(sc, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA, 0); - } URE_SETBIT_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, URE_RXDY_GATED_EN); ure_disable_teredo(sc); URE_CLRBIT_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, URE_RCR_ACPT_ALL); - if (sc->ure_flags & URE_FLAG_8156) - ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, 0); - else - ure_reset(sc); - + ure_reset(sc); ure_reset_bmu(sc); URE_CLRBIT_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA, URE_NOW_IS_OOB); URE_CLRBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_MCU_BORW_EN); - if (!(sc->ure_flags & URE_FLAG_8156)) { + if (!(sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B))) { for (i = 0; i < URE_TIMEOUT; i++) { if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & URE_LINK_LIST_READY) @@ -1430,65 +1487,89 @@ ure_rtl8153_nic_reset(struct ure_softc *sc) printf("%s: timeout waiting for OOB control\n", sc->ure_dev.dv_xname); } + ure_rxvlan(sc); + ure_write_2(sc, URE_PLA_RMS, URE_MCU_TYPE_PLA, URE_FRAMELEN(ifp->if_mtu)); ure_write_1(sc, URE_PLA_MTPS, URE_MCU_TYPE_PLA, MTPS_JUMBO); - if (!(sc->ure_flags & URE_FLAG_8156)) { + if (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { + ure_write_2(sc, URE_PLA_RX_FIFO_FULL, URE_MCU_TYPE_PLA, + (sc->ure_flags & URE_FLAG_8156) ? 1024 : 512); + ure_write_2(sc, URE_PLA_RX_FIFO_EMPTY, URE_MCU_TYPE_PLA, + (sc->ure_flags & URE_FLAG_8156) ? 2048 : 1024); + + /* Tx share fifo free credit full threshold. */ + ure_write_2(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, 8); + ure_write_2(sc, URE_PLA_TXFIFO_FULL, URE_MCU_TYPE_PLA, 128); + + if (sc->ure_flags & URE_FLAG_8156) + URE_SETBIT_2(sc, URE_USB_BMU_CONFIG, URE_MCU_TYPE_USB, + URE_ACT_ODMA); + + /* FIFO settings */ + reg = ure_read_2(sc, URE_PLA_RXFIFO_FULL, URE_MCU_TYPE_PLA); + reg &= ~URE_RXFIFO_FULL_MASK; + ure_write_2(sc, URE_PLA_RXFIFO_FULL, URE_MCU_TYPE_PLA, + reg | 0x0008); + + URE_CLRBIT_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, + URE_PLA_MCU_SPDWN_EN); + + URE_CLRBIT_2(sc, URE_USB_SPEED_OPTION, URE_MCU_TYPE_USB, + URE_RG_PWRDN_EN | URE_ALL_SPEED_OFF); + + ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, + 0x00600400); + } + + if (!(sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B))) { URE_SETBIT_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA, URE_TCR0_AUTO_FIFO); ure_reset(sc); - } - /* Configure Rx FIFO threshold. */ - if (sc->ure_flags & URE_FLAG_8156) { - ure_write_2(sc, URE_PLA_RXFIFO_CTRL0 + 2, URE_MCU_TYPE_PLA, - 0x0008); - ure_write_2(sc, URE_PLA_RXFIFO_CTRL1 + 2, URE_MCU_TYPE_PLA, - 0x0100); - ure_write_2(sc, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, 0); - } else { + /* Configure Rx FIFO threshold. */ ure_write_4(sc, URE_PLA_RXFIFO_CTRL0, URE_MCU_TYPE_PLA, URE_RXFIFO_THR1_NORMAL); ure_write_2(sc, URE_PLA_RXFIFO_CTRL1, URE_MCU_TYPE_PLA, URE_RXFIFO_THR2_NORMAL); ure_write_2(sc, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, URE_RXFIFO_THR3_NORMAL); - } - /* Configure Tx FIFO threshold. */ - ure_write_4(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, - URE_TXFIFO_THR_NORMAL2); + /* Configure Tx FIFO threshold. */ + ure_write_4(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, + URE_TXFIFO_THR_NORMAL2); - if (sc->ure_flags & URE_FLAG_8156) { - URE_CLRBIT_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, - 0x4000); - ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, - 0x00600400); - } else if (sc->ure_flags & URE_FLAG_8153B) { - ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, - URE_RX_THR_B); + if (sc->ure_flags & URE_FLAG_8153B) { + ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, + URE_RX_THR_B); + + URE_CLRBIT_2(sc, URE_PLA_MAC_PWR_CTRL3, + URE_MCU_TYPE_PLA, URE_PLA_MCU_SPDWN_EN); + } else { + URE_SETBIT_1(sc, URE_PLA_CONFIG6, URE_MCU_TYPE_PLA, + URE_LANWAKE_CLR_EN); + URE_CLRBIT_1(sc, URE_PLA_LWAKE_CTRL_REG, + URE_MCU_TYPE_PLA, URE_LANWAKE_PIN); + URE_CLRBIT_2(sc, URE_USB_SSPHYLINK1, URE_MCU_TYPE_USB, + URE_DELAY_PHY_PWR_CHG); + } } /* Enable ALDPS. */ ure_ocp_reg_write(sc, URE_OCP_POWER_CFG, ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) | URE_EN_ALDPS); - if (sc->ure_flags & URE_FLAG_8153B) { - reg = ure_read_4(sc, URE_USB_UPS_FLAGS, URE_MCU_TYPE_USB) & - URE_UPS_FLAGS_MASK; - ure_write_4(sc, URE_USB_UPS_FLAGS, URE_MCU_TYPE_USB, - reg | URE_UPS_FLAGS_EN_ALDPS); - } if ((sc->ure_chip & (URE_CHIP_VER_5C20 | URE_CHIP_VER_5C30)) || - (sc->ure_flags & (URE_FLAG_8153B | URE_FLAG_8156))) + (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B))) URE_SETBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE); - if (sc->ure_flags & (URE_FLAG_8153B | URE_FLAG_8156)) { - URE_SETBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, - LPM_U1U2_EN); + if (sc->ure_flags & (URE_FLAG_8153B | URE_FLAG_8156 | URE_FLAG_8156B)) { + if (sc->ure_udev->speed == USB_SPEED_SUPER) + URE_SETBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, + LPM_U1U2_EN); } else { memset(u1u2, 0xff, sizeof(u1u2)); ure_write_mem(sc, URE_USB_TOLERANCE, URE_BYTE_EN_SIX_BYTES, @@ -1496,8 +1577,8 @@ ure_rtl8153_nic_reset(struct ure_softc *sc) } } -void -ure_rtl8153_phy_status(struct ure_softc *sc, int enable) +uint16_t +ure_rtl8153_phy_status(struct ure_softc *sc, int desired) { uint16_t reg; int i; @@ -1505,8 +1586,8 @@ ure_rtl8153_phy_status(struct ure_softc *sc, int enable) for (i = 0; i < 500; i++) { reg = ure_ocp_reg_read(sc, URE_OCP_PHY_STATUS) & URE_PHY_STAT_MASK; - if (enable) { - if (reg == URE_PHY_STAT_LAN_ON) + if (desired) { + if (reg == desired) break; } else { if (reg == URE_PHY_STAT_LAN_ON || @@ -1519,21 +1600,47 @@ ure_rtl8153_phy_status(struct ure_softc *sc, int enable) if (i == 500) printf("%s: timeout waiting for phy to stabilize\n", sc->ure_dev.dv_xname); + + return reg; } - + +void +ure_wait_for_flash(struct ure_softc *sc) +{ + int i; + + if ((ure_read_2(sc, URE_PLA_GPHY_CTRL, URE_MCU_TYPE_PLA) & + URE_GPHY_FLASH) && + !(ure_read_2(sc, URE_USB_GPHY_CTRL, URE_MCU_TYPE_USB) & + URE_BYPASS_FLASH)) { + for (i = 0; i < 100; i++) { + if (ure_read_2(sc, URE_USB_GPHY_CTRL, + URE_MCU_TYPE_USB) & URE_GPHY_PATCH_DONE) + break; + DELAY(1000); + } + if (i == 100) + printf("%s: timeout waiting for loading flash\n", + sc->ure_dev.dv_xname); + } +} + void ure_reset_bmu(struct ure_softc *sc) { - URE_CLRBIT_1(sc, URE_USB_BMU_RESET, URE_MCU_TYPE_USB, - BMU_RESET_EP_IN | BMU_RESET_EP_OUT); - URE_SETBIT_1(sc, URE_USB_BMU_RESET, URE_MCU_TYPE_USB, - BMU_RESET_EP_IN | BMU_RESET_EP_OUT); + uint8_t reg; + + reg = ure_read_1(sc, URE_USB_BMU_RESET, URE_MCU_TYPE_USB); + reg &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT); + ure_write_1(sc, URE_USB_BMU_RESET, URE_MCU_TYPE_USB, reg); + reg |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT; + ure_write_1(sc, URE_USB_BMU_RESET, URE_MCU_TYPE_USB, reg); } void ure_disable_teredo(struct ure_softc *sc) { - if (sc->ure_flags & (URE_FLAG_8153B | URE_FLAG_8156)) + if (sc->ure_flags & (URE_FLAG_8153B | URE_FLAG_8156 | URE_FLAG_8156B)) ure_write_1(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA, 0xff); else { URE_CLRBIT_2(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA, @@ -1575,7 +1682,7 @@ ure_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) case SIOCGIFMEDIA: case SIOCSIFMEDIA: - if (sc->ure_flags & URE_FLAG_8156) + if (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) error = ifmedia_ioctl(ifp, ifr, &sc->ure_ifmedia, cmd); else error = ifmedia_ioctl(ifp, ifr, &sc->ure_mii.mii_media, @@ -1699,6 +1806,10 @@ ure_attach(struct device *parent, struct device *self, void *aux) sc->ure_flags = URE_FLAG_8156; printf("RTL8156 (0x7030)"); break; + case 0x7410: + sc->ure_flags = URE_FLAG_8156B; + printf("RTL8156B (0x7410)"); + break; default: printf(", unknown ver %02x", ver); break; @@ -1706,7 +1817,8 @@ ure_attach(struct device *parent, struct device *self, void *aux) if (sc->ure_flags & URE_FLAG_8152) ure_rtl8152_init(sc); - else if (sc->ure_flags & (URE_FLAG_8153B | URE_FLAG_8156)) + else if (sc->ure_flags & (URE_FLAG_8153B | URE_FLAG_8156 | + URE_FLAG_8156B)) ure_rtl8153b_init(sc); else ure_rtl8153_init(sc); @@ -1737,7 +1849,7 @@ ure_attach(struct device *parent, struct device *self, void *aux) ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; #endif - if (sc->ure_flags & URE_FLAG_8156) { + if (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { ifmedia_init(&sc->ure_ifmedia, IFM_IMASK, ure_ifmedia_upd, ure_ifmedia_sts); ure_add_media_types(sc); @@ -1830,7 +1942,7 @@ ure_tick_task(void *xsc) mii = &sc->ure_mii; s = splnet(); - if (sc->ure_flags & URE_FLAG_8156) + if (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) ure_link_state(sc); else { mii_tick(mii); @@ -1914,7 +2026,7 @@ ure_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) total_len -= roundup(pktlen, URE_RX_BUF_ALIGN); buf += sizeof(rxhdr); - m = m_devget(buf, pktlen, ETHER_ALIGN); + m = m_devget(buf, pktlen - ETHER_CRC_LEN, ETHER_ALIGN); if (m == NULL) { DPRINTF(("unable to allocate mbuf for next packet\n")); ifp->if_ierrors++; diff --git a/sys/dev/usb/if_urereg.h b/sys/dev/usb/if_urereg.h index fc2d183a8e6..47b7cdb3fb1 100644 --- a/sys/dev/usb/if_urereg.h +++ b/sys/dev/usb/if_urereg.h @@ -1,4 +1,4 @@ -/* $OpenBSD: if_urereg.h,v 1.10 2021/08/13 01:24:22 gnezdo Exp $ */ +/* $OpenBSD: if_urereg.h,v 1.11 2022/04/02 12:22:56 kevlo Exp $ */ /*- * Copyright (c) 2015, 2016, 2019 Kevin Lo * All rights reserved. @@ -50,10 +50,14 @@ #define URE_PLA_IDR 0xc000 #define URE_PLA_RCR 0xc010 +#define URE_PLA_RCR1 0xc012 #define URE_PLA_RMS 0xc016 #define URE_PLA_RXFIFO_CTRL0 0xc0a0 +#define URE_PLA_RXFIFO_FULL 0xc0a2 #define URE_PLA_RXFIFO_CTRL1 0xc0a4 +#define URE_PLA_RX_FIFO_FULL 0xc0a6 #define URE_PLA_RXFIFO_CTRL2 0xc0a8 +#define URE_PLA_RX_FIFO_EMPTY 0xc0aa #define URE_PLA_DMY_REG0 0xc0b0 #define URE_PLA_FMC 0xc0b4 #define URE_PLA_CFG_WOL 0xc0b6 @@ -66,10 +70,13 @@ #define URE_PLA_SUSPEND_FLAG 0xd38a #define URE_PLA_INDICATE_FALG 0xd38c #define URE_PLA_EXTRA_STATUS 0xd398 +#define URE_PLA_GPHY_CTRL 0xd3ae +#define URE_PLA_POL_GPIO_CTRL 0xdc6a #define URE_PLA_LEDSEL 0xdd90 #define URE_PLA_LED_FEATURE 0xdd92 #define URE_PLA_PHYAR 0xde00 #define URE_PLA_BOOT_CTRL 0xe004 +#define URE_PLA_LWAKE_CTRL_REG 0xe007 #define URE_PLA_GPHY_INTR_IMR 0xe022 #define URE_PLA_EEE_CR 0xe040 #define URE_PLA_EEEP_CR 0xe080 @@ -82,6 +89,7 @@ #define URE_PLA_TCR1 0xe612 #define URE_PLA_MTPS 0xe615 #define URE_PLA_TXFIFO_CTRL 0xe618 +#define URE_PLA_TXFIFO_FULL 0xe61a #define URE_PLA_RSTTALLY 0xe800 #define URE_PLA_CR 0xe813 #define URE_PLA_CRWECR 0xe81c @@ -96,8 +104,11 @@ #define URE_PLA_TELLYCNT 0xe890 #define URE_PLA_SFF_STS_7 0xe8de #define URE_PLA_PHYSTATUS 0xe908 +#define URE_PLA_CONFIG6 0xe90a +#define URE_PLA_USB_CFG 0xe952 #define URE_USB_USB2PHY 0xb41e +#define URE_USB_SSPHYLINK1 0xb426 #define URE_USB_SSPHYLINK2 0xb428 #define URE_USB_U2P3_CTRL 0xb460 #define URE_USB_CSR_DUMMY1 0xb464 @@ -107,6 +118,13 @@ #define URE_USB_MSC_TIMER 0xcbfc #define URE_USB_BURST_SIZE 0xcfc0 #define URE_USB_LPM_CONFIG 0xcfd8 +#define URE_USB_ECM_OPTION 0xcfee +#define URE_USB_MISC_2 0xcfff +#define URE_USB_ECM_OP 0xd26b +#define URE_USB_GPHY_CTRL 0xd284 +#define URE_USB_SPEED_OPTION 0xd32a +#define URE_USB_FW_CTRL 0xd334 +#define URE_USB_FC_TIMER 0xd340 #define URE_USB_USB_CTRL 0xd406 #define URE_USB_PHY_CTRL 0xd408 #define URE_USB_TX_AGG 0xd40a @@ -120,7 +138,10 @@ #define URE_USB_UPT_RXDMA_OWN 0xd437 #define URE_USB_TOLERANCE 0xd490 #define URE_USB_BMU_RESET 0xd4b0 +#define URE_USB_BMU_CONFIG 0xd4b4 #define URE_USB_U1U2_TIMER 0xd4da +#define URE_USB_FW_TASK 0xd4e8 +#define URE_USB_RX_AGGR_NUM 0xd4ee #define URE_USB_UPS_CTRL 0xd800 #define URE_USB_POWER_CUT 0xd80a #define URE_USB_MISC_0 0xd81a @@ -162,11 +183,19 @@ #define URE_RCR_AB 0x00000008 #define URE_RCR_ACPT_ALL \ (URE_RCR_AAP | URE_RCR_APM | URE_RCR_AM | URE_RCR_AB) +#define URE_SLOT_EN 0x00000800 + +/* URE_PLA_RCR1 */ +#define URE_INNER_VLAN 0x0040 +#define URE_OUTER_VLAN 0x0080 /* URE_PLA_RXFIFO_CTRL0 */ #define URE_RXFIFO_THR1_NORMAL 0x00080002 #define URE_RXFIFO_THR1_OOB 0x01800003 +/* URE_PLA_RXFIFO_FULL */ +#define URE_RXFIFO_FULL_MASK 0x0fff + /* URE_PLA_RXFIFO_CTRL1 */ #define URE_RXFIFO_THR2_FULL 0x00000060 #define URE_RXFIFO_THR2_HIGH 0x00000038 @@ -234,6 +263,7 @@ #define URE_RE_INIT_LL 0x8000 /* URE_PLA_CPCR */ +#define URE_FLOW_CTRL_EN 0x0001 #define URE_CPCR_RX_VLAN 0x0040 /* URE_PLA_TEREDO_CFG */ @@ -266,14 +296,16 @@ #define URE_ALDPS_SPDWN_RATIO 0x0f87 /* URE_PLA_MAC_PWR_CTRL2 */ -#define URE_MAC_CLK_SPDWN_EN 0x8000 -#define URE_EEE_SPDWN_RATIO 0x8007 +#define URE_MAC_CLK_SPDWN_EN 0x8000 +#define URE_EEE_SPDWN_RATIO 0x8007 +#define URE_EEE_SPDWN_RATIO_MASK 0x00ff /* URE_PLA_MAC_PWR_CTRL3 */ #define URE_L1_SPDWN_EN 0x0001 #define URE_U1U2_SPDWN_EN 0x0002 #define URE_SUSPEND_SPDWN_EN 0x0004 #define URE_PKT_AVAIL_SPDWN_EN 0x0100 +#define URE_PLA_MCU_SPDWN_EN 0x4000 /* URE_PLA_MAC_PWR_CTRL4 */ #define URE_EEE_SPDWN_EN 0x0001 @@ -301,6 +333,9 @@ /* URE_PLA_BOOT_CTRL */ #define URE_AUTOLOAD_DONE 0x0002 +/* URE_PLA_LWAKE_CTRL_REG */ +#define URE_LANWAKE_PIN 0x80 + /* URE_PLA_SUSPEND_FLAG */ #define URE_LINK_CHG_EVENT 0x01 @@ -308,7 +343,15 @@ #define URE_UPCOMING_RUNTIME_D3 0x01 /* URE_PLA_EXTRA_STATUS */ +#define URE_POLL_LINK_CHG 0x0001 #define URE_LINK_CHANGE_FLAG 0x0100 +#define URE_CUR_LINK_OK 0x8000 + +/* URE_PLA_GPHY_CTRL */ +#define URE_GPHY_FLASH 0x0002 + +/* URE_PLA_POL_GPIO_CTRL */ +#define URE_DACK_DET_EN 0x8000 /* URE_PLA_PHYSTATUS */ #define URE_PHYSTATUS_FDX 0x0001 @@ -318,10 +361,16 @@ #define URE_PHYSTATUS_1000MBPS 0x0010 #define URE_PHYSTATUS_2500MBPS 0x0400 +/* URE_PLA_CONFIG6 */ +#define URE_LANWAKE_CLR_EN 0x01 + /* URE_USB_USB2PHY */ #define URE_USB2PHY_SUSPEND 0x0001 #define URE_USB2PHY_L1 0x0002 +/* URE_USB_SSPHYLINK1 */ +#define URE_DELAY_PHY_PWR_CHG 0x0002 + /* URE_USB_SSPHYLINK2 */ #define URE_PWD_DN_SCALE_MASK 0x3ffe #define URE_PWD_DN_SCALE(x) ((x) << 1) @@ -340,6 +389,31 @@ /* URE_USB_LPM_CONFIG */ #define LPM_U1U2_EN 0x0001 +/* URE_USB_MISC_2 */ +#define URE_UPS_FORCE_PWR_DOWN 0x01 + +/* URE_USB_ECM_OPTION */ +#define URE_BYPASS_MAC_RESET 0x0020 + +/* URE_USB_GPHY_CTRL */ +#define URE_GPHY_PATCH_DONE 0x0004 +#define URE_BYPASS_FLASH 0x0020 + +/* URE_USB_SPEED_OPTION */ +#define URE_RG_PWRDN_EN 0x0100 +#define URE_ALL_SPEED_OFF 0x0200 + +/* URE_USB_FW_CTRL */ +#define URE_FLOW_CTRL_PATCH_OPT 0x0002 +#define URE_AUTO_SPEEDUP 0x0008 +#define URE_FLOW_CTRL_PATCH_2 0x0100 + +/* URE_URE_USB_FC_TIMER */ +#define URE_CTRL_TIMER_EN 0x8000 + +/* URE_USB_USB_ECM_OP */ +#define URE_EN_ALL_SPEED 0x0001 + /* URE_USB_TX_AGG */ #define URE_TX_AGG_MAX_THRESHOLD 0x03 @@ -361,6 +435,15 @@ #define BMU_RESET_EP_IN 0x01 #define BMU_RESET_EP_OUT 0x02 +/* URE_USB_BMU_CONFIG */ +#define URE_ACT_ODMA 0x02 + +/* URE_USB_FW_TASK */ +#define URE_FC_PATCH_TASK 0x0002 + +/* URE_USB_RX_AGGR_NUM */ +#define URE_RX_AGGR_NUM_MASK 0x1ff + /* URE_USB_UPS_CTRL */ #define URE_POWER_CUT 0x0100 @@ -368,11 +451,13 @@ #define URE_RESUME_INDICATE 0x0001 /* URE_USB_USB_CTRL */ +#define URE_CDC_ECM_EN 0x0008 #define URE_RX_AGG_DISABLE 0x0010 #define URE_RX_ZERO_EN 0x0080 /* URE_USB_U2P3_CTRL */ #define URE_U2P3_ENABLE 0x0001 +#define URE_RX_DETECT8 0x0008 /* URE_USB_POWER_CUT */ #define URE_PWR_EN 0x0001 @@ -551,6 +636,7 @@ struct ure_softc { #define URE_FLAG_8152 0x1000 /* RTL8152 */ #define URE_FLAG_8153B 0x2000 /* RTL8153B */ #define URE_FLAG_8156 0x4000 /* RTL8156 */ +#define URE_FLAG_8156B 0x8000 /* RTL8156B */ u_int ure_chip; #define URE_CHIP_VER_4C00 0x01 @@ -559,4 +645,5 @@ struct ure_softc { #define URE_CHIP_VER_5C10 0x08 #define URE_CHIP_VER_5C20 0x10 #define URE_CHIP_VER_5C30 0x20 +#define URE_CHIP_VER_6010 0x40 }; -- 2.20.1