From 7d4ece3a03ac10d34b2c62fe8c02e66334a575c4 Mon Sep 17 00:00:00 2001 From: drahn Date: Mon, 29 Aug 2022 01:34:18 +0000 Subject: [PATCH] Support full GICD SPI interrupt count for REG32/REG16. This enables SPI support for interrupts on X13s. ok jsg@ --- sys/arch/arm64/dev/agintc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/sys/arch/arm64/dev/agintc.c b/sys/arch/arm64/dev/agintc.c index ba96da80954..58404941f5d 100644 --- a/sys/arch/arm64/dev/agintc.c +++ b/sys/arch/arm64/dev/agintc.c @@ -1,4 +1,4 @@ -/* $OpenBSD: agintc.c,v 1.41 2022/08/03 13:36:51 kettenis Exp $ */ +/* $OpenBSD: agintc.c,v 1.42 2022/08/29 01:34:18 drahn Exp $ */ /* * Copyright (c) 2007, 2009, 2011, 2017 Dale Rahn * Copyright (c) 2018 Mark Kettenis @@ -130,10 +130,10 @@ #define SPI_BASE 32 #define LPI_BASE 8192 -#define IRQ_TO_REG32(i) (((i) >> 5) & 0x7) +#define IRQ_TO_REG32(i) (((i) >> 5) & 0x1f) #define IRQ_TO_REG32BIT(i) ((i) & 0x1f) -#define IRQ_TO_REG16(i) (((i) >> 4) & 0xf) +#define IRQ_TO_REG16(i) (((i) >> 4) & 0x3f) #define IRQ_TO_REG16BIT(i) ((i) & 0xf) #define IRQ_ENABLE 1 -- 2.20.1