From 715e2b8b1aeb512c8932e559d66748f45721414f Mon Sep 17 00:00:00 2001 From: jsg Date: Mon, 27 Mar 2023 04:10:36 +0000 Subject: [PATCH] drm/amd/display: Do not commit pipe when updating DRR From Wesley Chalmers d919f493bb7dc4d0b568039b728eb44ca961ebaa in linux-6.1.y/6.1.16 8f0d304d21b351d65e8c434c5399a40231876ba1 in mainline linux --- sys/dev/pci/drm/amd/display/dc/core/amdgpu_dc.c | 15 +++++++++++++++ sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_optc.h | 3 ++- sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_optc.c | 9 +++++++++ sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_optc.h | 2 ++ .../drm/amd/display/dc/inc/hw/timing_generator.h | 1 + 5 files changed, 29 insertions(+), 1 deletion(-) diff --git a/sys/dev/pci/drm/amd/display/dc/core/amdgpu_dc.c b/sys/dev/pci/drm/amd/display/dc/core/amdgpu_dc.c index 24015f8cac7..af7aefe285f 100644 --- a/sys/dev/pci/drm/amd/display/dc/core/amdgpu_dc.c +++ b/sys/dev/pci/drm/amd/display/dc/core/amdgpu_dc.c @@ -3222,6 +3222,21 @@ static void commit_planes_for_stream(struct dc *dc, dc_z10_restore(dc); + if (update_type == UPDATE_TYPE_FULL) { + /* wait for all double-buffer activity to clear on all pipes */ + int pipe_idx; + + for (pipe_idx = 0; pipe_idx < dc->res_pool->pipe_count; pipe_idx++) { + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx]; + + if (!pipe_ctx->stream) + continue; + + if (pipe_ctx->stream_res.tg->funcs->wait_drr_doublebuffer_pending_clear) + pipe_ctx->stream_res.tg->funcs->wait_drr_doublebuffer_pending_clear(pipe_ctx->stream_res.tg); + } + } + if (get_seamless_boot_stream_count(context) > 0 && surface_count > 0) { /* Optimize seamless boot flag keeps clocks and watermarks high until * first flip. After first flip, optimization is required to lower diff --git a/sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_optc.h b/sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_optc.h index f5020904c20..2a38562dda9 100644 --- a/sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_optc.h +++ b/sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_optc.h @@ -519,7 +519,8 @@ struct dcn_optc_registers { type OTG_CRC_DATA_STREAM_COMBINE_MODE;\ type OTG_CRC_DATA_STREAM_SPLIT_MODE;\ type OTG_CRC_DATA_FORMAT;\ - type OTG_V_TOTAL_LAST_USED_BY_DRR; + type OTG_V_TOTAL_LAST_USED_BY_DRR;\ + type OTG_DRR_TIMING_DBUF_UPDATE_PENDING; #define TG_REG_FIELD_LIST_DCN3_2(type) \ type OTG_H_TIMING_DIV_MODE_MANUAL; diff --git a/sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_optc.c b/sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_optc.c index 892d3c4d01a..25749f7d883 100644 --- a/sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_optc.c +++ b/sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_optc.c @@ -282,6 +282,14 @@ static void optc3_set_timing_double_buffer(struct timing_generator *optc, bool e OTG_DRR_TIMING_DBUF_UPDATE_MODE, mode); } +void optc3_wait_drr_doublebuffer_pending_clear(struct timing_generator *optc) +{ + struct optc *optc1 = DCN10TG_FROM_TG(optc); + + REG_WAIT(OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_PENDING, 0, 2, 100000); /* 1 vupdate at 5hz */ + +} + void optc3_set_vtotal_min_max(struct timing_generator *optc, int vtotal_min, int vtotal_max) { optc1_set_vtotal_min_max(optc, vtotal_min, vtotal_max); @@ -351,6 +359,7 @@ static struct timing_generator_funcs dcn30_tg_funcs = { .program_manual_trigger = optc2_program_manual_trigger, .setup_manual_trigger = optc2_setup_manual_trigger, .get_hw_timing = optc1_get_hw_timing, + .wait_drr_doublebuffer_pending_clear = optc3_wait_drr_doublebuffer_pending_clear, }; void dcn30_timing_generator_init(struct optc *optc1) diff --git a/sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_optc.h b/sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_optc.h index dd45a5499b0..fb06dc9a489 100644 --- a/sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_optc.h +++ b/sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_optc.h @@ -279,6 +279,7 @@ SF(OTG0_OTG_DRR_TRIGGER_WINDOW, OTG_DRR_TRIGGER_WINDOW_END_X, mask_sh),\ SF(OTG0_OTG_DRR_V_TOTAL_CHANGE, OTG_DRR_V_TOTAL_CHANGE_LIMIT, mask_sh),\ SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_BY2, mask_sh),\ + SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_PENDING, mask_sh),\ SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_MODE, mask_sh),\ SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_BLANK_DATA_DOUBLE_BUFFER_EN, mask_sh) @@ -317,6 +318,7 @@ SF(OTG0_OTG_DRR_TRIGGER_WINDOW, OTG_DRR_TRIGGER_WINDOW_END_X, mask_sh),\ SF(OTG0_OTG_DRR_V_TOTAL_CHANGE, OTG_DRR_V_TOTAL_CHANGE_LIMIT, mask_sh),\ SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, mask_sh),\ + SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_PENDING, mask_sh),\ SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_MODE, mask_sh) void dcn30_timing_generator_init(struct optc *optc1); diff --git a/sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h b/sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h index 91ddcc46593..06066809867 100644 --- a/sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h +++ b/sys/dev/pci/drm/amd/display/dc/inc/hw/timing_generator.h @@ -325,6 +325,7 @@ struct timing_generator_funcs { uint32_t vtotal_change_limit); void (*init_odm)(struct timing_generator *tg); + void (*wait_drr_doublebuffer_pending_clear)(struct timing_generator *tg); }; #endif -- 2.20.1