From 6e9149a4c720aadf58fd1dbbe87628696d9f2360 Mon Sep 17 00:00:00 2001 From: stsp Date: Wed, 11 Oct 2023 12:52:00 +0000 Subject: [PATCH] Add initial support for Elkhart Lake ethernet to dwqe(4). For now, only attach to PSE0/RGMII (device ID 0x4ba0) which is the only device I have access to for testing. There is a known problem where Tx throughput is lower than expected. This is being looked into. ok kettenis@ --- sys/arch/amd64/conf/GENERIC | 3 +- sys/dev/ic/dwqe.c | 33 ++++++-- sys/dev/ic/dwqevar.h | 4 +- sys/dev/pci/files.pci | 6 +- sys/dev/pci/if_dwqe_pci.c | 154 ++++++++++++++++++++++++++++++++++++ 5 files changed, 189 insertions(+), 11 deletions(-) create mode 100644 sys/dev/pci/if_dwqe_pci.c diff --git a/sys/arch/amd64/conf/GENERIC b/sys/arch/amd64/conf/GENERIC index c6094ca5a57..0aea3e6faed 100644 --- a/sys/arch/amd64/conf/GENERIC +++ b/sys/arch/amd64/conf/GENERIC @@ -1,4 +1,4 @@ -# $OpenBSD: GENERIC,v 1.519 2023/09/25 15:36:35 deraadt Exp $ +# $OpenBSD: GENERIC,v 1.520 2023/10/11 12:52:00 stsp Exp $ # # For further information on compiling OpenBSD kernels, see the config(8) # man page. @@ -556,6 +556,7 @@ lii* at pci? # Attansic L2 Ethernet jme* at pci? # JMicron JMC250/JMC260 Ethernet bnxt* at pci? # Broadcom BCM573xx, BCM574xx ixl* at pci? # Intel Ethernet 700 Series +dwqe* at pci? # Intel Elkhart Lake Ethernet mcx* at pci? # Mellanox ConnectX-4 iavf* at pci? # Intel Ethernet Adaptive VF aq* at pci? # Aquantia aQtion Ethernet diff --git a/sys/dev/ic/dwqe.c b/sys/dev/ic/dwqe.c index 7d260ef4605..33d7ab55043 100644 --- a/sys/dev/ic/dwqe.c +++ b/sys/dev/ic/dwqe.c @@ -1,4 +1,4 @@ -/* $OpenBSD: dwqe.c,v 1.13 2023/10/10 07:11:50 stsp Exp $ */ +/* $OpenBSD: dwqe.c,v 1.14 2023/10/11 12:52:00 stsp Exp $ */ /* * Copyright (c) 2008, 2019 Mark Kettenis * Copyright (c) 2017, 2022 Patrick Wildt @@ -705,7 +705,7 @@ dwqe_up(struct dwqe_softc *sc) { struct ifnet *ifp = &sc->sc_ac.ac_if; struct dwqe_buf *txb, *rxb; - uint32_t mode, reg, tqs, rqs; + uint32_t mode, reg, fifosz, tqs, rqs; int i; /* Allocate Tx descriptor ring. */ @@ -793,9 +793,21 @@ dwqe_up(struct dwqe_softc *sc) mode |= GMAC_MTL_CHAN_RX_OP_MODE_RSF; } mode &= ~GMAC_MTL_CHAN_RX_OP_MODE_RQS_MASK; - rqs = (128 << GMAC_MAC_HW_FEATURE1_RXFIFOSIZE(sc->sc_hw_feature[1]) / - 256) - 1; - mode |= rqs << GMAC_MTL_CHAN_RX_OP_MODE_RQS_SHIFT; + if (sc->sc_rxfifo_size) + fifosz = sc->sc_rxfifo_size; + else + fifosz = (128 << + GMAC_MAC_HW_FEATURE1_RXFIFOSIZE(sc->sc_hw_feature[1])); + rqs = fifosz / 256 - 1; + mode |= (rqs << GMAC_MTL_CHAN_RX_OP_MODE_RQS_SHIFT) & + GMAC_MTL_CHAN_RX_OP_MODE_RQS_MASK; + if (fifosz >= 4096) { + mode |= GMAC_MTL_CHAN_RX_OP_MODE_EHFC; + mode &= ~GMAC_MTL_CHAN_RX_OP_MODE_RFD_MASK; + mode |= 0x3 << GMAC_MTL_CHAN_RX_OP_MODE_RFD_SHIFT; + mode &= ~GMAC_MTL_CHAN_RX_OP_MODE_RFA_MASK; + mode |= 0x1 << GMAC_MTL_CHAN_RX_OP_MODE_RFA_SHIFT; + } dwqe_write(sc, GMAC_MTL_CHAN_RX_OP_MODE(0), mode); mode = dwqe_read(sc, GMAC_MTL_CHAN_TX_OP_MODE(0)); @@ -809,9 +821,14 @@ dwqe_up(struct dwqe_softc *sc) mode &= ~GMAC_MTL_CHAN_TX_OP_MODE_TXQEN_MASK; mode |= GMAC_MTL_CHAN_TX_OP_MODE_TXQEN; mode &= ~GMAC_MTL_CHAN_TX_OP_MODE_TQS_MASK; - tqs = (128 << GMAC_MAC_HW_FEATURE1_TXFIFOSIZE(sc->sc_hw_feature[1]) / - 256) - 1; - mode |= tqs << GMAC_MTL_CHAN_TX_OP_MODE_TQS_SHIFT; + if (sc->sc_txfifo_size) + fifosz = sc->sc_txfifo_size; + else + fifosz = (128 << + GMAC_MAC_HW_FEATURE1_TXFIFOSIZE(sc->sc_hw_feature[1])); + tqs = (fifosz / 256) - 1; + mode |= (tqs << GMAC_MTL_CHAN_TX_OP_MODE_TQS_SHIFT) & + GMAC_MTL_CHAN_TX_OP_MODE_TQS_MASK; dwqe_write(sc, GMAC_MTL_CHAN_TX_OP_MODE(0), mode); reg = dwqe_read(sc, GMAC_QX_TX_FLOW_CTRL(0)); diff --git a/sys/dev/ic/dwqevar.h b/sys/dev/ic/dwqevar.h index 68d698a50be..c5c7df5caa9 100644 --- a/sys/dev/ic/dwqevar.h +++ b/sys/dev/ic/dwqevar.h @@ -1,4 +1,4 @@ -/* $OpenBSD: dwqevar.h,v 1.8 2023/10/10 07:11:50 stsp Exp $ */ +/* $OpenBSD: dwqevar.h,v 1.9 2023/10/11 12:52:00 stsp Exp $ */ /* * Copyright (c) 2008, 2019 Mark Kettenis * Copyright (c) 2017, 2022 Patrick Wildt @@ -97,6 +97,8 @@ struct dwqe_softc { int sc_pbl; int sc_txpbl; int sc_rxpbl; + int sc_txfifo_size; + int sc_rxfifo_size; int sc_axi_config; int sc_lpi_en; int sc_xit_frm; diff --git a/sys/dev/pci/files.pci b/sys/dev/pci/files.pci index 101ed502e76..022a04a88bd 100644 --- a/sys/dev/pci/files.pci +++ b/sys/dev/pci/files.pci @@ -1,4 +1,4 @@ -# $OpenBSD: files.pci,v 1.361 2023/04/23 00:20:26 dlg Exp $ +# $OpenBSD: files.pci,v 1.362 2023/10/11 12:52:00 stsp Exp $ # $NetBSD: files.pci,v 1.20 1996/09/24 17:47:15 christos Exp $ # # Config file and device description for machine-independent PCI code. @@ -363,6 +363,10 @@ device ixl: ether, ifnet, ifmedia, intrmap, stoeplitz attach ixl at pci file dev/pci/if_ixl.c ixl +# Intel Elkhart Lake Ethernet +attach dwqe at pci with dwqe_pci +file dev/pci/if_dwqe_pci.c dwqe_pci + # Neterion Xframe 10 Gigabit ethernet device xge: ether, ifnet, ifmedia attach xge at pci diff --git a/sys/dev/pci/if_dwqe_pci.c b/sys/dev/pci/if_dwqe_pci.c new file mode 100644 index 00000000000..757e47c55d2 --- /dev/null +++ b/sys/dev/pci/if_dwqe_pci.c @@ -0,0 +1,154 @@ +/* $OpenBSD: if_dwqe_pci.c,v 1.1 2023/10/11 12:52:01 stsp Exp $ */ + +/* + * Copyright (c) 2023 Stefan Sperling + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +/* + * Driver for the Intel Elkhart Lake ethernet controller. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#if NBPFILTER > 0 +#include +#endif +#include +#include +#include + +#include +#include + +#include +#include + +#include +#include + +static const struct pci_matchid dwqe_pci_devices[] = { + { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EHL_PSE0_RGMII_1G }, +#if 0 + { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EHL_PSE0_SGMII_1G }, + { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EHL_PSE0_SGMII_2G }, + { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EHL_PSE1_RGMII_1G }, + { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EHL_PSE1_SGMII_1G }, + { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EHL_PSE1_SGMII_2G }, +#endif +}; + +struct dwqe_pci_softc { + struct dwqe_softc sc_sc; + pci_chipset_tag_t sc_pct; + pcitag_t sc_pcitag; + bus_size_t sc_mapsize; +}; + +int +dwqe_pci_match(struct device *parent, void *cfdata, void *aux) +{ + struct pci_attach_args *pa = aux; + return pci_matchbyid(pa, dwqe_pci_devices, nitems(dwqe_pci_devices)); +} + +void +dwqe_pci_attach(struct device *parent, struct device *self, void *aux) +{ + struct pci_attach_args *pa = aux; + struct dwqe_pci_softc *psc = (void *)self; + struct dwqe_softc *sc = &psc->sc_sc; + pci_intr_handle_t ih; + pcireg_t memtype; + int err; + const char *intrstr; + + psc->sc_pct = pa->pa_pc; + psc->sc_pcitag = pa->pa_tag; + + sc->sc_dmat = pa->pa_dmat; + + memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, PCI_MAPREG_START); + err = pci_mapreg_map(pa, PCI_MAPREG_START, memtype, 0, + &sc->sc_iot, &sc->sc_ioh, NULL, &psc->sc_mapsize, 0); + if (err) { + printf("%s: can't map mem space\n", DEVNAME(sc)); + return; + } + + if (pci_intr_map_msi(pa, &ih) && pci_intr_map(pa, &ih)) { + printf("%s: can't map interrupt\n", DEVNAME(sc)); + return; + } + + intrstr = pci_intr_string(psc->sc_pct, ih); + sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_NET | IPL_MPSAFE, + dwqe_intr, psc, sc->sc_dev.dv_xname); + if (sc->sc_ih == NULL) { + printf(": can't establish interrupt"); + if (intrstr != NULL) + printf(" at %s", intrstr); + printf("\n"); + return; + } + + switch (PCI_PRODUCT(pa->pa_id)) { + case PCI_PRODUCT_INTEL_EHL_PSE0_RGMII_1G: + sc->sc_phy_mode = DWQE_PHY_MODE_RGMII_ID; + sc->sc_clk = GMAC_MAC_MDIO_ADDR_CR_250_300; + sc->sc_clkrate = 200000000; + break; + default: + sc->sc_phy_mode = DWQE_PHY_MODE_UNKNOWN; + break; + } + + sc->sc_phyloc = MII_PHY_ANY; + sc->sc_8xpbl = 1; + sc->sc_txpbl = 32; + sc->sc_rxpbl = 32; + sc->sc_txfifo_size = 32768; + sc->sc_rxfifo_size = 32768; + + sc->sc_axi_config = 1; + sc->sc_wr_osr_lmt = 1; + sc->sc_rd_osr_lmt = 1; + sc->sc_blen[0] = 4; + sc->sc_blen[1] = 8; + sc->sc_blen[2] = 16; + + dwqe_lladdr_read(sc, sc->sc_lladdr); + + dwqe_reset(sc); + dwqe_attach(sc); +} + +const struct cfattach dwqe_pci_ca = { + sizeof(struct dwqe_softc), dwqe_pci_match, dwqe_pci_attach +}; -- 2.20.1