From 6555b60d244562935d9c4f120483e72453f9273d Mon Sep 17 00:00:00 2001
From: patrick <patrick@openbsd.org>
Date: Mon, 1 Apr 2024 11:16:11 +0000
Subject: [PATCH] Add clocks for the RK3588 PWM controller.

ok kettenis@
---
 sys/dev/fdt/rkclock.c        | 17 ++++++++++++++++-
 sys/dev/fdt/rkclock_clocks.h |  3 +++
 2 files changed, 19 insertions(+), 1 deletion(-)

diff --git a/sys/dev/fdt/rkclock.c b/sys/dev/fdt/rkclock.c
index e7ee863951c..81aca118463 100644
--- a/sys/dev/fdt/rkclock.c
+++ b/sys/dev/fdt/rkclock.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: rkclock.c,v 1.87 2024/03/06 14:55:22 kettenis Exp $	*/
+/*	$OpenBSD: rkclock.c,v 1.88 2024/04/01 11:16:11 patrick Exp $	*/
 /*
  * Copyright (c) 2017, 2018 Mark Kettenis <kettenis@openbsd.org>
  *
@@ -3917,6 +3917,21 @@ rk3568_pmu_reset(void *cookie, uint32_t *cells, int on)
  */
 
 const struct rkclock rk3588_clocks[] = {
+	{
+		RK3588_CLK_PWM1, RK3588_CRU_CLKSEL_CON(59),
+		SEL(13, 12), 0,
+		{ RK3588_CLK_100M_SRC, RK3588_CLK_50M_SRC, RK3588_XIN24M },
+	},
+	{
+		RK3588_CLK_PWM2, RK3588_CRU_CLKSEL_CON(59),
+		SEL(15, 14), 0,
+		{ RK3588_CLK_100M_SRC, RK3588_CLK_50M_SRC, RK3588_XIN24M },
+	},
+	{
+		RK3588_CLK_PWM3, RK3588_CRU_CLKSEL_CON(60),
+		SEL(1, 0), 0,
+		{ RK3588_CLK_100M_SRC, RK3588_CLK_50M_SRC, RK3588_XIN24M },
+	},
 	{
 		RK3588_ACLK_BUS_ROOT, RK3588_CRU_CLKSEL_CON(38),
 		SEL(5, 5), DIV(4, 0),
diff --git a/sys/dev/fdt/rkclock_clocks.h b/sys/dev/fdt/rkclock_clocks.h
index 7a593c44791..793c1a02103 100644
--- a/sys/dev/fdt/rkclock_clocks.h
+++ b/sys/dev/fdt/rkclock_clocks.h
@@ -410,6 +410,9 @@
 #define RK3588_PLL_NPLL			7
 #define RK3588_PLL_PPLL			8
 
+#define RK3588_CLK_PWM1			76
+#define RK3588_CLK_PWM2			79
+#define RK3588_CLK_PWM3			82
 #define RK3588_ACLK_BUS_ROOT		113
 #define RK3588_CLK_I2C1			131
 #define RK3588_CLK_I2C2			132
-- 
2.20.1