From 6198737ba9dd09e7f08f94c46d1b353879eb49c1 Mon Sep 17 00:00:00 2001 From: jsg Date: Mon, 29 Apr 2024 06:30:19 +0000 Subject: [PATCH] drm/i915/mst: Limit MST+DSC to TGL+ From Ville Syrjala 75170320459ae5bedf73352989b8433880cba20a in linux-6.6.y/6.6.29 51bc63392e96ca45d7be98bc43c180b174ffca09 in mainline linux --- sys/dev/pci/drm/i915/display/intel_display_device.h | 1 + sys/dev/pci/drm/i915/display/intel_dp_mst.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/sys/dev/pci/drm/i915/display/intel_display_device.h b/sys/dev/pci/drm/i915/display/intel_display_device.h index a0613de9b7c..1cda039e501 100644 --- a/sys/dev/pci/drm/i915/display/intel_display_device.h +++ b/sys/dev/pci/drm/i915/display/intel_display_device.h @@ -47,6 +47,7 @@ struct drm_printer; #define HAS_DPT(i915) (DISPLAY_VER(i915) >= 13) #define HAS_DSB(i915) (DISPLAY_INFO(i915)->has_dsb) #define HAS_DSC(__i915) (DISPLAY_RUNTIME_INFO(__i915)->has_dsc) +#define HAS_DSC_MST(__i915) (DISPLAY_VER(__i915) >= 12 && HAS_DSC(__i915)) #define HAS_FBC(i915) (DISPLAY_RUNTIME_INFO(i915)->fbc_mask != 0) #define HAS_FPGA_DBG_UNCLAIMED(i915) (DISPLAY_INFO(i915)->has_fpga_dbg) #define HAS_FW_BLC(i915) (DISPLAY_VER(i915) > 2) diff --git a/sys/dev/pci/drm/i915/display/intel_dp_mst.c b/sys/dev/pci/drm/i915/display/intel_dp_mst.c index f104bd7f8c2..d2f8f20722d 100644 --- a/sys/dev/pci/drm/i915/display/intel_dp_mst.c +++ b/sys/dev/pci/drm/i915/display/intel_dp_mst.c @@ -964,7 +964,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector, return 0; } - if (DISPLAY_VER(dev_priv) >= 10 && + if (HAS_DSC_MST(dev_priv) && drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) { /* * TBD pass the connector BPC, -- 2.20.1