From 6150e7082e0bd0464b45c9c00a0009624b0de6cb Mon Sep 17 00:00:00 2001 From: jsg Date: Thu, 23 Feb 2023 02:17:38 +0000 Subject: [PATCH] drm/amd/display: Reset DMUB mailbox SW state after HW reset From Nicholas Kazlauskas 488770cbddd8a873fb3bb8866e8a46211570c367 in linux-6.1.y/6.1.13 154711aa5759ef9b45903124fa813c4c29ee681c in mainline linux --- sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c b/sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c index 4a122925c3a..92c18bfb98b 100644 --- a/sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c +++ b/sys/dev/pci/drm/amd/display/dmub/src/dmub_srv.c @@ -532,6 +532,9 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub, if (dmub->hw_funcs.reset) dmub->hw_funcs.reset(dmub); + /* reset the cache of the last wptr as well now that hw is reset */ + dmub->inbox1_last_wptr = 0; + cw0.offset.quad_part = inst_fb->gpu_addr; cw0.region.base = DMUB_CW0_BASE; cw0.region.top = cw0.region.base + inst_fb->size - 1; @@ -649,6 +652,15 @@ enum dmub_status dmub_srv_hw_reset(struct dmub_srv *dmub) if (dmub->hw_funcs.reset) dmub->hw_funcs.reset(dmub); + /* mailboxes have been reset in hw, so reset the sw state as well */ + dmub->inbox1_last_wptr = 0; + dmub->inbox1_rb.wrpt = 0; + dmub->inbox1_rb.rptr = 0; + dmub->outbox0_rb.wrpt = 0; + dmub->outbox0_rb.rptr = 0; + dmub->outbox1_rb.wrpt = 0; + dmub->outbox1_rb.rptr = 0; + dmub->hw_init = false; return DMUB_STATUS_OK; -- 2.20.1