From 4f0183c801faf589199b345284b042ba185379b1 Mon Sep 17 00:00:00 2001 From: guenther Date: Thu, 13 Jun 2024 02:19:20 +0000 Subject: [PATCH] Wrong variable used in indexing meant that when a CPU's cache setup differed on the second or later cache, the generated dmesg didn't report the earlier, identical cache levels correctly. report, testing, and ok jsg@ --- sys/arch/amd64/amd64/cacheinfo.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/sys/arch/amd64/amd64/cacheinfo.c b/sys/arch/amd64/amd64/cacheinfo.c index f89eda55b48..41fba9f3e80 100644 --- a/sys/arch/amd64/amd64/cacheinfo.c +++ b/sys/arch/amd64/amd64/cacheinfo.c @@ -1,4 +1,4 @@ -/* $OpenBSD: cacheinfo.c,v 1.14 2024/05/08 18:00:55 guenther Exp $ */ +/* $OpenBSD: cacheinfo.c,v 1.15 2024/06/13 02:19:20 guenther Exp $ */ /* * Copyright (c) 2022 Jonathan Gray @@ -246,8 +246,8 @@ intel_print_cacheinfo(struct cpu_info *ci, u_int fn) } /* print lower levels that were the same */ for (i = 0; i < leaf; i++) - intel_print_one_cache(ci, i, prev_cache[leaf][0], - prev_cache[leaf][1], prev_cache[leaf][2]); + intel_print_one_cache(ci, i, prev_cache[i][0], + prev_cache[i][1], prev_cache[i][2]); /* print this (differing) level and higher levels */ goto printit; } -- 2.20.1