From 4c00a306fa0078e8a7c66a5010760adcb9b41b0b Mon Sep 17 00:00:00 2001 From: jsg Date: Sat, 29 Jan 2022 12:40:27 +0000 Subject: [PATCH] drm/amd/display: reset dcn31 SMU mailbox on failures From Mario Limonciello f71c91ed1d4b4bfbbb55327b04dcc32b2d970f62 in linux 5.15.y/5.15.18 83293f7f3d15fc56e86bd5067a2c88b6b233ac3a in mainline linux --- sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c b/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c index f7f58d4605b..2bfa13e3abe 100644 --- a/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c +++ b/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c @@ -119,6 +119,12 @@ int dcn31_smu_send_msg_with_param( result = dcn31_smu_wait_for_response(clk_mgr, 10, 200000); + if (result == VBIOSSMC_Result_Failed) { + ASSERT(0); + REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Result_OK); + return -1; + } + if (IS_SMU_TIMEOUT(result)) { ASSERT(0); dm_helpers_smu_timeout(CTX, msg_id, param, 10 * 200000); -- 2.20.1