From 4525f0e0071f72c5f30a145f894a77e2f187820a Mon Sep 17 00:00:00 2001 From: jsg Date: Sun, 7 Jun 2015 16:54:16 +0000 Subject: [PATCH] Initial exynos4 bits. Among other things the gic isn't mapped correctly on exynos4/5 yet as it isn't at the usual offset from periphbase. ok bmercer@ --- sys/arch/armv7/armv7/armv7var.h | 4 +- sys/arch/armv7/exynos/exynos.c | 64 ++++- sys/arch/armv7/exynos/exynos4.c | 323 +++++++++++++++++++++++++ sys/arch/armv7/exynos/exynos_machdep.c | 8 +- sys/arch/armv7/exynos/files.exynos | 3 +- 5 files changed, 398 insertions(+), 4 deletions(-) create mode 100644 sys/arch/armv7/exynos/exynos4.c diff --git a/sys/arch/armv7/armv7/armv7var.h b/sys/arch/armv7/armv7/armv7var.h index 87ac2d116dc..1c2f14a6e02 100644 --- a/sys/arch/armv7/armv7/armv7var.h +++ b/sys/arch/armv7/armv7/armv7var.h @@ -1,4 +1,4 @@ -/* $OpenBSD: armv7var.h,v 1.7 2015/05/24 11:06:16 jsg Exp $ */ +/* $OpenBSD: armv7var.h,v 1.8 2015/06/07 16:54:16 jsg Exp $ */ /* * Copyright (c) 2005,2008 Dale Rahn * Copyright (c) 2012-2013 Patrick Wildt @@ -78,6 +78,8 @@ int armv7_submatch(struct device *, void *, void *); #define BOARD_ID_OMAP3_BEAGLE 1546 #define BOARD_ID_OMAP3_OVERO 1798 #define BOARD_ID_OMAP4_PANDA 2791 +#define BOARD_ID_EXYNOS4_SMDKC210 2838 +#define BOARD_ID_EXYNOS4_NURI 3379 #define BOARD_ID_IMX6_PHYFLEX 3529 #define BOARD_ID_AM335X_BEAGLEBONE 3589 #define BOARD_ID_IMX6_SABRELITE 3769 diff --git a/sys/arch/armv7/exynos/exynos.c b/sys/arch/armv7/exynos/exynos.c index 06369bb1125..5e62c482038 100644 --- a/sys/arch/armv7/exynos/exynos.c +++ b/sys/arch/armv7/exynos/exynos.c @@ -1,4 +1,4 @@ -/* $OpenBSD: exynos.c,v 1.6 2015/05/27 00:06:14 jsg Exp $ */ +/* $OpenBSD: exynos.c,v 1.7 2015/06/07 16:54:16 jsg Exp $ */ /* * Copyright (c) 2005,2008 Dale Rahn * Copyright (c) 2012-2013 Patrick Wildt @@ -29,6 +29,7 @@ #include int exynos_match(struct device *, void *, void *); +void exynos4_init(); void exynos5_init(); struct cfattach exynos_ca = { @@ -60,6 +61,55 @@ struct board_dev chromebook_devs[] = { { NULL, 0 } }; +/* Samsung Mobile NURI board */ +struct board_dev nuri_devs[] = { + { "exmct", 0 }, + { "exdog", 0 }, +// { "exclock", 0 }, + { "expower", 0 }, + { "exsysreg", 0 }, +// { "exuart", 0 }, + { "exuart", 1 }, + { "exuart", 2 }, + { "exuart", 3 }, + { "exgpio", 0 }, + { "exgpio", 1 }, + { "exgpio", 2 }, + { "exgpio", 3 }, + { "exgpio", 4 }, + { "exgpio", 5 }, +// { "exehci", 0 }, + { "exiic", 0 }, +// { "exesdhc", 2 }, + { NULL, 0 } +}; + +/* + * S5PC210/Exynos4210 reference board + * has a LAN9215 (emulated in qemu as LAN9118) + */ +struct board_dev smdkc210_devs[] = { + { "exmct", 0 }, + { "exdog", 0 }, +// { "exclock", 0 }, + { "expower", 0 }, + { "exsysreg", 0 }, +// { "exuart", 0 }, + { "exuart", 1 }, + { "exuart", 2 }, + { "exuart", 3 }, + { "exgpio", 0 }, + { "exgpio", 1 }, + { "exgpio", 2 }, + { "exgpio", 3 }, + { "exgpio", 4 }, + { "exgpio", 5 }, +// { "exehci", 0 }, + { "exiic", 0 }, +// { "exesdhc", 2 }, + { NULL, 0 } +}; + struct armv7_board exynos_boards[] = { { BOARD_ID_EXYNOS5_CHROMEBOOK, @@ -67,6 +117,18 @@ struct armv7_board exynos_boards[] = { chromebook_devs, exynos5_init, }, + { + BOARD_ID_EXYNOS4_NURI, + "Samsung NURI", + nuri_devs, + exynos4_init, + }, + { + BOARD_ID_EXYNOS4_SMDKC210, + "Samsung SMDKC210", + smdkc210_devs, + exynos4_init, + }, { 0, NULL, NULL, NULL }, }; diff --git a/sys/arch/armv7/exynos/exynos4.c b/sys/arch/armv7/exynos/exynos4.c new file mode 100644 index 00000000000..9ca18d2fb26 --- /dev/null +++ b/sys/arch/armv7/exynos/exynos4.c @@ -0,0 +1,323 @@ +/* $OpenBSD: exynos4.c,v 1.1 2015/06/07 16:54:16 jsg Exp $ */ +/* + * Copyright (c) 2011 Uwe Stuehler + * Copyright (c) 2012 Patrick Wildt + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include +#include +#include +#include +#include + +#include + +/* IRQs are defined without the 32 cpu IRQs */ + +#define MCT_ADDR 0x10050000 +#define MCT_SIZE 0x800 + +#define WD_ADDR 0x10060000 +#define WD_SIZE 0x400 +#define WD_IRQ 43 + +#define CLOCK_ADDR 0x10030000 +#define CLOCK_SIZE 0x20000 + +#define POWER_ADDR 0x10020000 +#define POWER_SIZE 0x4000 + +#define SYSREG_ADDR 0x10010000 +#define SYSREG_SIZE 0x400 + +#define UARTx_SIZE 0x100 +#define UART1_ADDR 0x13800000 +#define UART2_ADDR 0x13810000 +#define UART3_ADDR 0x13820000 +#define UART4_ADDR 0x13830000 +#define UART5_ADDR 0x13840000 + +#define UART1_IRQ 52 +#define UART2_IRQ 53 +#define UART3_IRQ 54 +#define UART4_IRQ 55 +#define UART5_IRQ 56 + +#define USB_EHCI_ADDR 0x12580000 +#define USB_OHCI_ADDR 0x12590000 +#define USB_PHY_ADDR 0x125b0000 +#define USBx_SIZE 0x1000 + +#define USB_IRQ 70 + +#define GPIO1_ADDR 0x11400000 +#define GPIO1_SIZE 0x280 +#define GPIO2_ADDR 0x11400C00 +#define GPIO2_SIZE 0x80 +#define GPIO3_ADDR 0x13400000 +#define GPIO3_SIZE 0x120 +#define GPIO4_ADDR 0x10D10000 +#define GPIO4_SIZE 0x80 +#define GPIO5_ADDR 0x10D100C0 +#define GPIO5_SIZE 0x20 +#define GPIO6_ADDR 0x03860000 +#define GPIO6_SIZE 0x20 + +#define I2Cx_SIZE 0x100 +#define I2C1_ADDR 0x13860000 +#define I2C2_ADDR 0x13870000 +#define I2C3_ADDR 0x13880000 +#define I2C4_ADDR 0x13890000 +#define I2C5_ADDR 0x138a0000 +#define I2C6_ADDR 0x138b0000 +#define I2C7_ADDR 0x138c0000 +#define I2C8_ADDR 0x138d0000 + +#define I2C1_IRQ 58 +#define I2C2_IRQ 59 +#define I2C3_IRQ 60 +#define I2C4_IRQ 61 +#define I2C5_IRQ 62 +#define I2C6_IRQ 63 +#define I2C7_IRQ 64 +#define I2C8_IRQ 65 + +#define ESDHCx_SIZE 0x1000 +#define ESDHC1_ADDR 0x12510000 +#define ESDHC2_ADDR 0x12520000 +#define ESDHC3_ADDR 0x12530000 +#define ESDHC4_ADDR 0x12540000 + +#define ESDHC1_IRQ 73 +#define ESDHC2_IRQ 74 +#define ESDHC3_IRQ 75 +#define ESDHC4_IRQ 76 +#define SDMMC_IRQ 77 + +struct armv7_dev exynos4_devs[] = { + + /* + * Multi-Core Timer + */ + { .name = "exmct", + .unit = 0, + .mem = { + { MCT_ADDR, MCT_SIZE }, + }, + }, + + /* + * Watchdog Timer + */ + { .name = "exdog", + .unit = 0, + .mem = { + { WD_ADDR, WD_SIZE }, + }, + }, + + /* + * Clock + */ + { .name = "exclock", + .unit = 0, + .mem = { + { CLOCK_ADDR, CLOCK_SIZE }, + }, + }, + + /* + * Power + */ + { .name = "expower", + .unit = 0, + .mem = { + { POWER_ADDR, POWER_SIZE }, + }, + }, + + /* + * Sysreg + */ + { .name = "exsysreg", + .unit = 0, + .mem = { + { SYSREG_ADDR, SYSREG_SIZE }, + }, + }, + + /* + * UART + */ + { .name = "exuart", + .unit = 0, + .mem = { { UART1_ADDR, UARTx_SIZE } }, + .irq = { UART1_IRQ } + }, + { .name = "exuart", + .unit = 1, + .mem = { { UART2_ADDR, UARTx_SIZE } }, + .irq = { UART2_IRQ } + }, + { .name = "exuart", + .unit = 2, + .mem = { { UART3_ADDR, UARTx_SIZE } }, + .irq = { UART3_IRQ } + }, + { .name = "exuart", + .unit = 3, + .mem = { { UART4_ADDR, UARTx_SIZE } }, + .irq = { UART4_IRQ } + }, + { .name = "exuart", + .unit = 4, + .mem = { { UART5_ADDR, UARTx_SIZE } }, + .irq = { UART5_IRQ } + }, + + /* + * GPIO + */ + { .name = "exgpio", + .unit = 0, + .mem = { { GPIO1_ADDR, GPIO1_SIZE } }, + }, + + { .name = "exgpio", + .unit = 1, + .mem = { { GPIO2_ADDR, GPIO2_SIZE } }, + }, + + { .name = "exgpio", + .unit = 2, + .mem = { { GPIO3_ADDR, GPIO3_SIZE } }, + }, + + { .name = "exgpio", + .unit = 3, + .mem = { { GPIO4_ADDR, GPIO4_SIZE } }, + }, + + { .name = "exgpio", + .unit = 4, + .mem = { { GPIO5_ADDR, GPIO5_SIZE } }, + }, + + { .name = "exgpio", + .unit = 5, + .mem = { { GPIO6_ADDR, GPIO6_SIZE } }, + }, + + /* + * I2C + */ + { .name = "exiic", + .unit = 0, + .mem = { { I2C1_ADDR, I2Cx_SIZE } }, + .irq = { I2C1_IRQ }, + }, + + { .name = "exiic", + .unit = 1, + .mem = { { I2C2_ADDR, I2Cx_SIZE } }, + .irq = { I2C2_IRQ }, + }, + + { .name = "exiic", + .unit = 2, + .mem = { { I2C3_ADDR, I2Cx_SIZE } }, + .irq = { I2C3_IRQ }, + }, + + { .name = "exiic", + .unit = 3, + .mem = { { I2C4_ADDR, I2Cx_SIZE } }, + .irq = { I2C4_IRQ }, + }, + + { .name = "exiic", + .unit = 4, + .mem = { { I2C5_ADDR, I2Cx_SIZE } }, + .irq = { I2C5_IRQ }, + }, + + { .name = "exiic", + .unit = 5, + .mem = { { I2C6_ADDR, I2Cx_SIZE } }, + .irq = { I2C6_IRQ }, + }, + + { .name = "exiic", + .unit = 6, + .mem = { { I2C7_ADDR, I2Cx_SIZE } }, + .irq = { I2C7_IRQ }, + }, + + { .name = "exiic", + .unit = 7, + .mem = { { I2C8_ADDR, I2Cx_SIZE } }, + .irq = { I2C8_IRQ }, + }, + + /* + * ESDHC + */ + { .name = "exesdhc", + .unit = 0, + .mem = { { ESDHC1_ADDR, ESDHCx_SIZE } }, + .irq = { ESDHC1_IRQ }, + }, + + { .name = "exesdhc", + .unit = 1, + .mem = { { ESDHC2_ADDR, ESDHCx_SIZE } }, + .irq = { ESDHC2_IRQ }, + }, + + { .name = "exesdhc", + .unit = 2, + .mem = { { ESDHC3_ADDR, ESDHCx_SIZE } }, + .irq = { ESDHC3_IRQ }, + }, + + { .name = "exesdhc", + .unit = 3, + .mem = { { ESDHC4_ADDR, ESDHCx_SIZE } }, + .irq = { ESDHC4_IRQ }, + }, + + /* + * USB + */ + { .name = "exehci", + .unit = 0, + .mem = { + { USB_EHCI_ADDR, USBx_SIZE }, + { USB_PHY_ADDR, USBx_SIZE }, + }, + .irq = { USB_IRQ } + }, + + /* Terminator */ + { .name = NULL, + .unit = 0 + } +}; + +void +exynos4_init(void) +{ + armv7_set_devs(exynos4_devs); +} diff --git a/sys/arch/armv7/exynos/exynos_machdep.c b/sys/arch/armv7/exynos/exynos_machdep.c index 76665a8b6c4..b41f76933e3 100644 --- a/sys/arch/armv7/exynos/exynos_machdep.c +++ b/sys/arch/armv7/exynos/exynos_machdep.c @@ -1,4 +1,4 @@ -/* $OpenBSD: exynos_machdep.c,v 1.4 2015/05/27 00:06:14 jsg Exp $ */ +/* $OpenBSD: exynos_machdep.c,v 1.5 2015/06/07 16:54:16 jsg Exp $ */ /* * Copyright (c) 2013 Patrick Wildt * @@ -32,6 +32,7 @@ #include #include #include +#include #include extern void exdog_reset(void); @@ -72,6 +73,11 @@ exynos_platform_init_cons(void) #endif exdisplay_cnattach(&armv7_bs_tag, paddr, size); break; + case BOARD_ID_EXYNOS4_SMDKC210: + case BOARD_ID_EXYNOS4_NURI: + paddr = 0x13800000; + exuartcnattach(&armv7_bs_tag, paddr, comcnspeed, comcnmode); + break; default: printf("board type %x unknown", board_id); return; diff --git a/sys/arch/armv7/exynos/files.exynos b/sys/arch/armv7/exynos/files.exynos index 48f571dcef8..ef53213e34e 100644 --- a/sys/arch/armv7/exynos/files.exynos +++ b/sys/arch/armv7/exynos/files.exynos @@ -1,10 +1,11 @@ -# $OpenBSD: files.exynos,v 1.1 2015/01/26 02:48:24 bmercer Exp $ +# $OpenBSD: files.exynos,v 1.2 2015/06/07 16:54:16 jsg Exp $ define exynos {} device exynos: exynos attach exynos at mainbus file arch/armv7/exynos/exynos_machdep.c exynos needs-flag file arch/armv7/exynos/exynos.c exynos +file arch/armv7/exynos/exynos4.c exynos file arch/armv7/exynos/exynos5.c exynos # serial ports -- 2.20.1