From 3e8d5ed726b786f354cacf7c3804ba83a01c83ca Mon Sep 17 00:00:00 2001 From: miod Date: Mon, 18 Aug 2014 17:23:06 +0000 Subject: [PATCH] Sigh, ignoring instruction fetch bus errors for the kernel code should not depend upon the address being at the beginning of a cache line, for we may arrive in the middle of a line thanks to a branch. Noticed the hard way... --- sys/arch/mips64/mips64/trap.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/sys/arch/mips64/mips64/trap.c b/sys/arch/mips64/mips64/trap.c index 86449bfe4c2..783a8c0de76 100644 --- a/sys/arch/mips64/mips64/trap.c +++ b/sys/arch/mips64/mips64/trap.c @@ -1,4 +1,4 @@ -/* $OpenBSD: trap.c,v 1.99 2014/08/17 11:11:34 miod Exp $ */ +/* $OpenBSD: trap.c,v 1.100 2014/08/18 17:23:06 miod Exp $ */ /* * Copyright (c) 1988 University of Utah. @@ -793,8 +793,7 @@ fault_common_no_miss: * look like an obscure errata to me). * * Thus, ignore these exceptions if the faulting address - * is in the kernel and at the beginning of an I$ cache - * line. + * is in the kernel. */ { extern void *kernel_text; @@ -804,8 +803,7 @@ fault_common_no_miss: va = (vaddr_t)trapframe->pc; if (trapframe->cause & CR_BR_DELAY) va += 4; - if ((va & (/* R10K_L1I_LINE - 1 */ 64UL - 1)) == 0 && - va > (vaddr_t)&kernel_text && va < (vaddr_t)&etext) + if (va > (vaddr_t)&kernel_text && va < (vaddr_t)&etext) return; } goto err; -- 2.20.1