From 3e1f83d482c648ae31e3eeaaa98c7035c3040844 Mon Sep 17 00:00:00 2001 From: jsg Date: Mon, 9 Sep 2024 08:51:04 +0000 Subject: [PATCH] drm/amd/display: Check num_valid_sets before accessing reader_wm_sets[] From Alex Hung 21f9cb44f8c60bf6c26487d428b1a09ad3e8aebf in linux-6.6.y/6.6.50 b38a4815f79b87efb196cd5121579fc51e29a7fb in mainline linux --- sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c index 0c6a4ab72b1..97cdc24cef9 100644 --- a/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c +++ b/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c @@ -484,7 +484,8 @@ static void build_watermark_ranges(struct clk_bw_params *bw_params, struct pp_sm ranges->reader_wm_sets[num_valid_sets].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; /* Modify previous watermark range to cover up to max */ - ranges->reader_wm_sets[num_valid_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; + if (num_valid_sets > 0) + ranges->reader_wm_sets[num_valid_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; } num_valid_sets++; } -- 2.20.1