From 3b46785e07b766a006ba1c3273e9c4853ce6f500 Mon Sep 17 00:00:00 2001 From: jsg Date: Fri, 2 Feb 2024 03:41:53 +0000 Subject: [PATCH] drm/amdgpu/gfx11: set UNORD_DISPATCH in compute MQDs From Alex Deucher 5ff487d180dc25138d2261dda9e3b2d46ef3051a in linux-6.6.y/6.6.15 3380fcad2c906872110d31ddf7aa1fdea57f9df6 in mainline linux --- sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c | 2 +- sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v11.c | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c b/sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c index e11eb916ccb..25203311ded 100644 --- a/sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c +++ b/sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c @@ -3807,7 +3807,7 @@ static int gfx_v11_0_compute_mqd_init(struct amdgpu_device *adev, void *m, (order_base_2(prop->queue_size / 4) - 1)); tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); - tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); diff --git a/sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v11.c b/sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v11.c index 15277f1d5cf..d722cbd3178 100644 --- a/sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v11.c +++ b/sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v11.c @@ -224,6 +224,7 @@ static void update_mqd(struct mqd_manager *mm, void *mqd, m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; m->cp_hqd_pq_control |= ffs(q->queue_size / sizeof(unsigned int)) - 1 - 1; + m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK; pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); -- 2.20.1