From 31414e4ed3959a96c26e66084735218a74e03260 Mon Sep 17 00:00:00 2001 From: jsg Date: Thu, 1 Jan 2015 03:26:13 +0000 Subject: [PATCH] Always drain the write buffer on pte sync. Needed for Cortex A7/A15 which have integrated L2 so changes will get flushed to memory ASAP. From Patrick Wildt in Bitrig via rapha@ ok miod@ --- sys/arch/arm/include/pmap.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/sys/arch/arm/include/pmap.h b/sys/arch/arm/include/pmap.h index da4bd58da87..21b7afcd7a0 100644 --- a/sys/arch/arm/include/pmap.h +++ b/sys/arch/arm/include/pmap.h @@ -1,4 +1,4 @@ -/* $OpenBSD: pmap.h,v 1.28 2014/11/16 12:30:56 deraadt Exp $ */ +/* $OpenBSD: pmap.h,v 1.29 2015/01/01 03:26:13 jsg Exp $ */ /* $NetBSD: pmap.h,v 1.76 2003/09/06 09:10:46 rearnsha Exp $ */ /* @@ -328,9 +328,9 @@ extern int pmap_needs_pte_sync; #define PTE_SYNC(pte) \ do { \ + cpu_drain_writebuf(); \ if (PMAP_NEEDS_PTE_SYNC) { \ paddr_t pa; \ - cpu_drain_writebuf(); \ cpu_dcache_wb_range((vaddr_t)(pte), sizeof(pt_entry_t));\ if (cpu_sdcache_enabled()) { \ (void)pmap_extract(pmap_kernel(), (vaddr_t)(pte), &pa); \ @@ -343,9 +343,9 @@ do { \ #define PTE_SYNC_RANGE(pte, cnt) \ do { \ + cpu_drain_writebuf(); \ if (PMAP_NEEDS_PTE_SYNC) { \ paddr_t pa; \ - cpu_drain_writebuf(); \ cpu_dcache_wb_range((vaddr_t)(pte), \ (cnt) << 2); /* * sizeof(pt_entry_t) */ \ if (cpu_sdcache_enabled()) { \ -- 2.20.1