From 285e3455f19744964261b71b66d9c75f75d20405 Mon Sep 17 00:00:00 2001 From: kettenis Date: Thu, 13 May 2021 19:26:25 +0000 Subject: [PATCH] Use intr_enable()/int_disable()/intr_restore() instead of enable_interrupts()/disable_interrupts()/restore_interrupts() and remove the latter interfaces. ok mlarkin@, drahn@ --- sys/arch/riscv64/dev/plic.c | 24 +++++++++++-------- sys/arch/riscv64/dev/riscv_cpu_intc.c | 22 ++++++++---------- sys/arch/riscv64/include/intr.h | 33 +-------------------------- sys/arch/riscv64/riscv64/intr.c | 20 ++++++++-------- sys/arch/riscv64/riscv64/machdep.c | 4 ++-- sys/arch/riscv64/riscv64/pmap.c | 8 +++---- sys/arch/riscv64/riscv64/syscall.c | 4 ++-- 7 files changed, 43 insertions(+), 72 deletions(-) diff --git a/sys/arch/riscv64/dev/plic.c b/sys/arch/riscv64/dev/plic.c index 29985fbe781..e495b537e77 100644 --- a/sys/arch/riscv64/dev/plic.c +++ b/sys/arch/riscv64/dev/plic.c @@ -1,4 +1,4 @@ -/* $OpenBSD: plic.c,v 1.5 2021/05/13 09:32:00 kettenis Exp $ */ +/* $OpenBSD: plic.c,v 1.6 2021/05/13 19:26:25 kettenis Exp $ */ /* * Copyright (c) 2020, Mars Li @@ -405,12 +405,11 @@ plic_intr_establish(int irqno, int level, int (*func)(void *), { struct plic_softc *sc = plic; struct plic_intrhand *ih; - int sie; + u_long sie; if (irqno < 0 || irqno >= PLIC_MAX_IRQS) panic("plic_intr_establish: bogus irqnumber %d: %s", irqno, name); - sie = disable_interrupts(); ih = malloc(sizeof *ih, M_DEVBUF, M_WAITOK); ih->ih_func = func; @@ -420,6 +419,8 @@ plic_intr_establish(int irqno, int level, int (*func)(void *), ih->ih_irq = irqno; ih->ih_name = name; + sie = intr_disable(); + TAILQ_INSERT_TAIL(&sc->sc_isrcs[irqno].is_list, ih, ih_list); if (name != NULL) @@ -432,7 +433,7 @@ plic_intr_establish(int irqno, int level, int (*func)(void *), plic_calc_mask(); - restore_interrupts(sie); + intr_restore(sie); return (ih); } @@ -449,14 +450,17 @@ plic_intr_disestablish(void *cookie) struct plic_softc *sc = plic; struct plic_intrhand *ih = cookie; int irqno = ih->ih_irq; - int sie; + u_long sie; + + sie = intr_disable(); - sie = disable_interrupts(); TAILQ_REMOVE(&sc->sc_isrcs[irqno].is_list, ih, ih_list); if (ih->ih_name != NULL) evcount_detach(&ih->ih_count); + + intr_restore(sie); + free(ih, M_DEVBUF, 0); - restore_interrupts(sie); } void @@ -532,16 +536,16 @@ void plic_setipl(int new) { struct cpu_info *ci = curcpu(); - uint64_t sie; + u_long sie; /* disable here is only to keep hardware in sync with ci->ci_cpl */ - sie = disable_interrupts(); + sie = intr_disable(); ci->ci_cpl = new; /* higher values are higher priority */ plic_set_threshold(ci->ci_cpuid, new); - restore_interrupts(sie); + intr_restore(sie); } /* diff --git a/sys/arch/riscv64/dev/riscv_cpu_intc.c b/sys/arch/riscv64/dev/riscv_cpu_intc.c index 3955575e137..7f4f78e82fa 100644 --- a/sys/arch/riscv64/dev/riscv_cpu_intc.c +++ b/sys/arch/riscv64/dev/riscv_cpu_intc.c @@ -1,4 +1,4 @@ -/* $OpenBSD: riscv_cpu_intc.c,v 1.6 2021/05/12 01:20:52 jsg Exp $ */ +/* $OpenBSD: riscv_cpu_intc.c,v 1.7 2021/05/13 19:26:25 kettenis Exp $ */ /* * Copyright (c) 2020, Mars Li @@ -97,7 +97,7 @@ riscv_intc_attach(struct device *parent, struct device *self, void *aux) * XXX right time to enable interrupts ?? * might need to postpone untile autoconf is finished */ - enable_interrupts(); + intr_enable(); } @@ -130,13 +130,12 @@ void * riscv_intc_intr_establish(int irqno, int dummy_level, int (*func)(void *), void *arg, char *name) { - int sie; struct intrhand *ih; + u_long sie; if (irqno < 0 || irqno >= INTC_NIRQS) panic("intc_intr_establish: bogus irqnumber %d: %s", irqno, name); - sie = disable_interrupts(); ih = malloc(sizeof(*ih), M_DEVBUF, M_WAITOK); ih->ih_func = func; @@ -144,24 +143,23 @@ riscv_intc_intr_establish(int irqno, int dummy_level, int (*func)(void *), ih->ih_irq = irqno; ih->ih_name = name; + sie = intr_disable(); intc_handler[irqno] = ih; -#ifdef DEBUG_INTC - printf("\nintc_intr_establish irq %d [%s]\n", irqno, name); -#endif - restore_interrupts(sie); + intr_restore(sie); + return (ih); } void riscv_intc_intr_disestablish(void *cookie) { - int sie; struct intrhand *ih = cookie; int irqno = ih->ih_irq; - sie = disable_interrupts(); + u_long sie; + sie = intr_disable(); intc_handler[irqno] = NULL; - free(ih, M_DEVBUF, 0); + intr_restore(sie); - restore_interrupts(sie); + free(ih, M_DEVBUF, 0); } diff --git a/sys/arch/riscv64/include/intr.h b/sys/arch/riscv64/include/intr.h index 613a472b64a..6cb462e7b6d 100644 --- a/sys/arch/riscv64/include/intr.h +++ b/sys/arch/riscv64/include/intr.h @@ -1,4 +1,4 @@ -/* $OpenBSD: intr.h,v 1.3 2021/05/12 01:20:52 jsg Exp $ */ +/* $OpenBSD: intr.h,v 1.4 2021/05/13 19:26:25 kettenis Exp $ */ /* * Copyright (c) 2001-2004 Opsycon AB (www.opsycon.se / www.opsycon.com) @@ -150,37 +150,6 @@ extern struct riscv_intr_func riscv_intr_func; void intr_barrier(void *); -static inline void -enable_interrupts(void) -{ - __asm volatile( - "csrsi sstatus, %0" - :: "i" (SSTATUS_SIE) - ); -} - -static inline uint64_t -disable_interrupts(void) -{ - uint64_t ret; - - __asm volatile( - "csrrci %0, sstatus, %1" - : "=&r" (ret) : "i" (SSTATUS_SIE) - ); - - return (ret & (SSTATUS_SIE)); -} - -static inline void -restore_interrupts(uint64_t s) -{ - __asm volatile( - "csrs sstatus, %0" - :: "r" (s & (SSTATUS_SIE)) - ); -} - void riscv_init_smask(void); /* XXX */ extern uint32_t riscv_smask[NIPL]; diff --git a/sys/arch/riscv64/riscv64/intr.c b/sys/arch/riscv64/riscv64/intr.c index 1d31e250108..f4babfaf317 100644 --- a/sys/arch/riscv64/riscv64/intr.c +++ b/sys/arch/riscv64/riscv64/intr.c @@ -1,4 +1,4 @@ -/* $OpenBSD: intr.c,v 1.4 2021/05/12 01:20:52 jsg Exp $ */ +/* $OpenBSD: intr.c,v 1.5 2021/05/13 19:26:25 kettenis Exp $ */ /* * Copyright (c) 2011 Dale Rahn @@ -404,18 +404,18 @@ void riscv_do_pending_intr(int pcpl) { struct cpu_info *ci = curcpu(); - int sie; + u_long sie; - sie = disable_interrupts(); + sie = intr_disable(); #define DO_SOFTINT(si, ipl) \ if ((ci->ci_ipending & riscv_smask[pcpl]) & \ - SI_TO_IRQBIT(si)) { \ - ci->ci_ipending &= ~SI_TO_IRQBIT(si); \ - riscv_intr_func.setipl(ipl); \ - restore_interrupts(sie); \ - softintr_dispatch(si); \ - sie = disable_interrupts(); \ + SI_TO_IRQBIT(si)) { \ + ci->ci_ipending &= ~SI_TO_IRQBIT(si); \ + riscv_intr_func.setipl(ipl); \ + intr_restore(sie); \ + softintr_dispatch(si); \ + sie = intr_disable(); \ } do { @@ -427,7 +427,7 @@ riscv_do_pending_intr(int pcpl) /* Don't use splx... we are here already! */ riscv_intr_func.setipl(pcpl); - restore_interrupts(sie); + intr_restore(sie); } void riscv_set_intr_func(int (*raise)(int), int (*lower)(int), diff --git a/sys/arch/riscv64/riscv64/machdep.c b/sys/arch/riscv64/riscv64/machdep.c index f872510c12f..e271e6b4380 100644 --- a/sys/arch/riscv64/riscv64/machdep.c +++ b/sys/arch/riscv64/riscv64/machdep.c @@ -1,4 +1,4 @@ -/* $OpenBSD: machdep.c,v 1.14 2021/05/12 01:20:52 jsg Exp $ */ +/* $OpenBSD: machdep.c,v 1.15 2021/05/13 19:26:25 kettenis Exp $ */ /* * Copyright (c) 2014 Patrick Wildt @@ -202,7 +202,7 @@ void cpu_idle_cycle(void) { // Enable interrupts - enable_interrupts(); + intr_enable(); // XXX Data Sync Barrier? (Maybe SFENCE???) __asm volatile("wfi"); } diff --git a/sys/arch/riscv64/riscv64/pmap.c b/sys/arch/riscv64/riscv64/pmap.c index 2d9a6a64554..d48eb73a205 100644 --- a/sys/arch/riscv64/riscv64/pmap.c +++ b/sys/arch/riscv64/riscv64/pmap.c @@ -1,4 +1,4 @@ -/* $OpenBSD: pmap.c,v 1.7 2021/05/12 01:20:52 jsg Exp $ */ +/* $OpenBSD: pmap.c,v 1.8 2021/05/13 19:26:25 kettenis Exp $ */ /* * Copyright (c) 2019-2020 Brian Bamsch @@ -1425,12 +1425,12 @@ void pmap_activate(struct proc *p) { pmap_t pm = p->p_vmspace->vm_map.pmap; - int sie; + u_long sie; - sie = disable_interrupts(); + sie = intr_disable(); if (p == curproc && pm != curcpu()->ci_curpm) pmap_set_satp(p); - restore_interrupts(sie); + intr_restore(sie); } /* diff --git a/sys/arch/riscv64/riscv64/syscall.c b/sys/arch/riscv64/riscv64/syscall.c index bfc26f44fff..19ee7a1923d 100644 --- a/sys/arch/riscv64/riscv64/syscall.c +++ b/sys/arch/riscv64/riscv64/syscall.c @@ -1,4 +1,4 @@ -/* $OpenBSD: syscall.c,v 1.4 2021/05/12 01:20:52 jsg Exp $ */ +/* $OpenBSD: syscall.c,v 1.5 2021/05/13 19:26:25 kettenis Exp $ */ /* * Copyright (c) 2020 Brian Bamsch @@ -56,7 +56,7 @@ svc_handler(trapframe_t *frame) /* Re-enable interrupts if they were enabled previously */ if (__predict_true(frame->tf_scause & EXCP_INTR)) - enable_interrupts(); + intr_enable(); ap = &frame->tf_a[0]; // Pointer to first arg code = frame->tf_t[0]; // Syscall code -- 2.20.1