From 268d98527ef70a6de8a0fcdc976fd42f9efc0a15 Mon Sep 17 00:00:00 2001 From: jsg Date: Mon, 29 Jan 2024 01:27:31 +0000 Subject: [PATCH] drm/radeon/r600_cs: Fix possible int overflows in r600_cs_check_reg() From Nikita Zhandarovich 0413e8869171145d8a53f9d009f59c804b37c7b2 in linux-6.6.y/6.6.14 39c960bbf9d9ea862398759e75736cfb68c3446f in mainline linux --- sys/dev/pci/drm/radeon/r600_cs.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/sys/dev/pci/drm/radeon/r600_cs.c b/sys/dev/pci/drm/radeon/r600_cs.c index 638f861af80..6cf54a74774 100644 --- a/sys/dev/pci/drm/radeon/r600_cs.c +++ b/sys/dev/pci/drm/radeon/r600_cs.c @@ -1275,7 +1275,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) return -EINVAL; } tmp = (reg - CB_COLOR0_BASE) / 4; - track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8; + track->cb_color_bo_offset[tmp] = (u64)radeon_get_ib_value(p, idx) << 8; ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); track->cb_color_base_last[tmp] = ib[idx]; track->cb_color_bo[tmp] = reloc->robj; @@ -1302,7 +1302,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) "0x%04X\n", reg); return -EINVAL; } - track->htile_offset = radeon_get_ib_value(p, idx) << 8; + track->htile_offset = (u64)radeon_get_ib_value(p, idx) << 8; ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); track->htile_bo = reloc->robj; track->db_dirty = true; -- 2.20.1