From 1d46a334bde522d02becdab98c2219fa9c78ab64 Mon Sep 17 00:00:00 2001
From: jsg <jsg@openbsd.org>
Date: Sun, 2 Jan 2022 01:01:04 +0000
Subject: [PATCH] establush -> establish

---
 sys/arch/arm64/arm64/intr.c     | 4 ++--
 sys/arch/armv7/armv7/intr.c     | 4 ++--
 sys/arch/riscv64/riscv64/intr.c | 4 ++--
 3 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/sys/arch/arm64/arm64/intr.c b/sys/arch/arm64/arm64/intr.c
index af50223cd30..e3e8d46d552 100644
--- a/sys/arch/arm64/arm64/intr.c
+++ b/sys/arch/arm64/arm64/intr.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: intr.c,v 1.23 2021/05/17 17:25:13 kettenis Exp $ */
+/* $OpenBSD: intr.c,v 1.24 2022/01/02 01:01:04 jsg Exp $ */
 /*
  * Copyright (c) 2011 Dale Rahn <drahn@openbsd.org>
  *
@@ -182,7 +182,7 @@ out:
  * register a dummy interrupt controller that simply stashes away all
  * relevant details of the interrupt handler being established.
  * Later, when the real interrupt controller registers itself, we
- * establush those interrupt handlers based on that information.
+ * establish those interrupt handlers based on that information.
  */
 
 #define MAX_INTERRUPT_CELLS	4
diff --git a/sys/arch/armv7/armv7/intr.c b/sys/arch/armv7/armv7/intr.c
index 12986ce4d0b..c0816da3d83 100644
--- a/sys/arch/armv7/armv7/intr.c
+++ b/sys/arch/armv7/armv7/intr.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: intr.c,v 1.19 2021/03/11 11:16:56 jsg Exp $ */
+/* $OpenBSD: intr.c,v 1.20 2022/01/02 01:01:04 jsg Exp $ */
 /*
  * Copyright (c) 2011 Dale Rahn <drahn@openbsd.org>
  *
@@ -177,7 +177,7 @@ out:
  * register a dummy interrupt controller that simply stashes away all
  * relevant details of the interrupt handler being established.
  * Later, when the real interrupt controller registers itself, we
- * establush those interrupt handlers based on that information.
+ * establish those interrupt handlers based on that information.
  */
 
 #define MAX_INTERRUPT_CELLS	4
diff --git a/sys/arch/riscv64/riscv64/intr.c b/sys/arch/riscv64/riscv64/intr.c
index 23f77d230a7..9fbba867cc2 100644
--- a/sys/arch/riscv64/riscv64/intr.c
+++ b/sys/arch/riscv64/riscv64/intr.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: intr.c,v 1.8 2021/06/29 21:27:53 kettenis Exp $	*/
+/*	$OpenBSD: intr.c,v 1.9 2022/01/02 01:01:04 jsg Exp $	*/
 
 /*
  * Copyright (c) 2011 Dale Rahn <drahn@openbsd.org>
@@ -162,7 +162,7 @@ out:
  * register a dummy interrupt controller that simply stashes away all
  * relevant details of the interrupt handler being established.
  * Later, when the real interrupt controller registers itself, we
- * establush those interrupt handlers based on that information.
+ * establish those interrupt handlers based on that information.
  */
 
 #define MAX_INTERRUPT_CELLS	4
-- 
2.20.1