From 1cad7fde648fa748f63fbc7b813b97af0542d097 Mon Sep 17 00:00:00 2001 From: visa Date: Mon, 31 Oct 2022 13:59:10 +0000 Subject: [PATCH] mips64: Raise SPL for hardclock() This lets the MI clock interrupt code see the correct SPL. The full splx() is skipped because the updating of the hardware interrupt masks should not be needed here. Prompted by and OK cheloha@ --- sys/arch/mips64/mips64/clock.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/sys/arch/mips64/mips64/clock.c b/sys/arch/mips64/mips64/clock.c index 0eb1c16201b..3a0aae58c7f 100644 --- a/sys/arch/mips64/mips64/clock.c +++ b/sys/arch/mips64/mips64/clock.c @@ -1,4 +1,4 @@ -/* $OpenBSD: clock.c,v 1.46 2022/08/22 00:35:06 cheloha Exp $ */ +/* $OpenBSD: clock.c,v 1.47 2022/10/31 13:59:10 visa Exp $ */ /* * Copyright (c) 2001-2004 Opsycon AB (www.opsycon.se / www.opsycon.com) @@ -102,6 +102,7 @@ cp0_int5(uint32_t mask, struct trapframe *tf) { u_int32_t clkdiff, pendingticks = 0; struct cpu_info *ci = curcpu(); + int s; /* * If we got an interrupt before we got ready to process it, @@ -152,6 +153,7 @@ cp0_int5(uint32_t mask, struct trapframe *tf) /* * Process clock interrupt. */ + s = splclock(); #ifdef MULTIPROCESSOR register_t sr; @@ -166,6 +168,7 @@ cp0_int5(uint32_t mask, struct trapframe *tf) #ifdef MULTIPROCESSOR setsr(sr); #endif + ci->ci_ipl = s; return CR_INT_5; /* Clock is always on 5 */ } -- 2.20.1