From 18ec4e5466dd53da2eeb7a0b8e02317403c3460d Mon Sep 17 00:00:00 2001
From: yasuoka <yasuoka@openbsd.org>
Date: Fri, 4 Oct 2024 05:22:10 +0000
Subject: [PATCH] Expose {T,R}X desc trail and add link_enabled field to
 prepare VF support.  diff from naito.yuichiro at gmail.com

ok jan jmatthew
---
 sys/dev/pci/if_ix.c | 22 +++++++++++++---------
 sys/dev/pci/if_ix.h |  5 ++++-
 2 files changed, 17 insertions(+), 10 deletions(-)

diff --git a/sys/dev/pci/if_ix.c b/sys/dev/pci/if_ix.c
index 0d6ac83bd9f..dc5f8b641b2 100644
--- a/sys/dev/pci/if_ix.c
+++ b/sys/dev/pci/if_ix.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: if_ix.c,v 1.217 2024/09/04 07:54:52 mglocker Exp $	*/
+/*	$OpenBSD: if_ix.c,v 1.218 2024/10/04 05:22:10 yasuoka Exp $	*/
 
 /******************************************************************************
 
@@ -508,8 +508,7 @@ ixgbe_start(struct ifqueue *ifq)
 	 * hardware that this frame is available to transmit.
 	 */
 	if (post)
-		IXGBE_WRITE_REG(&sc->hw, IXGBE_TDT(txr->me),
-		    txr->next_avail_desc);
+		IXGBE_WRITE_REG(&sc->hw, txr->tail, txr->next_avail_desc);
 }
 
 /*********************************************************************
@@ -706,7 +705,7 @@ ixgbe_watchdog(struct ifnet * ifp)
 	for (i = 0; i < sc->num_queues; i++, txr++) {
 		printf("%s: Queue(%d) tdh = %d, hw tdt = %d\n", ifp->if_xname, i,
 		    IXGBE_READ_REG(hw, IXGBE_TDH(i)),
-		    IXGBE_READ_REG(hw, IXGBE_TDT(i)));
+		    IXGBE_READ_REG(hw, sc->tx_rings[i].tail));
 		printf("%s: TX(%d) Next TX to Clean = %d\n", ifp->if_xname,
 		    i, txr->next_to_clean);
 	}
@@ -826,7 +825,7 @@ ixgbe_init(void *arg)
 				msec_delay(1);
 		}
 		IXGBE_WRITE_FLUSH(&sc->hw);
-		IXGBE_WRITE_REG(&sc->hw, IXGBE_RDT(i), rxr->last_desc_filled);
+		IXGBE_WRITE_REG(&sc->hw, rxr[i].tail, rxr->last_desc_filled);
 	}
 
 	/* Set up VLAN support and filter */
@@ -2365,9 +2364,12 @@ ixgbe_initialize_transmit_units(struct ix_softc *sc)
 		IXGBE_WRITE_REG(hw, IXGBE_TDLEN(i),
 		    sc->num_tx_desc * sizeof(struct ixgbe_legacy_tx_desc));
 
+		/* Set Tx Tail register */
+		txr->tail = IXGBE_TDT(i);
+
 		/* Setup the HW Tx Head and Tail descriptor pointers */
 		IXGBE_WRITE_REG(hw, IXGBE_TDH(i), 0);
-		IXGBE_WRITE_REG(hw, IXGBE_TDT(i), 0);
+		IXGBE_WRITE_REG(hw, txr->tail, 0);
 
 		/* Setup Transmit Descriptor Cmd Settings */
 		txr->txd_cmd = IXGBE_TXD_CMD_IFCS;
@@ -2844,8 +2846,7 @@ ixgbe_rxrefill(void *xrxr)
 
 	if (ixgbe_rxfill(rxr)) {
 		/* Advance the Rx Queue "Tail Pointer" */
-		IXGBE_WRITE_REG(&sc->hw, IXGBE_RDT(rxr->me),
-		    rxr->last_desc_filled);
+		IXGBE_WRITE_REG(&sc->hw, rxr->tail, rxr->last_desc_filled);
 	} else if (if_rxr_inuse(&rxr->rx_ring) == 0)
 		timeout_add(&rxr->rx_refill, 1);
 
@@ -2940,6 +2941,9 @@ ixgbe_initialize_receive_units(struct ix_softc *sc)
 		srrctl = bufsz | IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
 		IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(i), srrctl);
 
+		/* Capture Rx Tail index */
+		rxr->tail = IXGBE_RDT(i);
+
 		if (ISSET(ifp->if_xflags, IFXF_LRO)) {
 			rdrxctl = IXGBE_READ_REG(&sc->hw, IXGBE_RSCCTL(i));
 
@@ -2952,7 +2956,7 @@ ixgbe_initialize_receive_units(struct ix_softc *sc)
 
 		/* Setup the HW Rx Head and Tail Descriptor Pointers */
 		IXGBE_WRITE_REG(hw, IXGBE_RDH(i), 0);
-		IXGBE_WRITE_REG(hw, IXGBE_RDT(i), 0);
+		IXGBE_WRITE_REG(hw, rxr->tail, 0);
 	}
 
 	if (sc->hw.mac.type != ixgbe_mac_82598EB) {
diff --git a/sys/dev/pci/if_ix.h b/sys/dev/pci/if_ix.h
index c1fc256d936..2cf82519312 100644
--- a/sys/dev/pci/if_ix.h
+++ b/sys/dev/pci/if_ix.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: if_ix.h,v 1.47 2024/05/21 11:19:39 bluhm Exp $	*/
+/*	$OpenBSD: if_ix.h,v 1.48 2024/10/04 05:22:10 yasuoka Exp $	*/
 
 /******************************************************************************
 
@@ -169,6 +169,7 @@ struct ix_txring {
 	struct ix_softc		*sc;
 	struct ifqueue		*ifq;
 	uint32_t		me;
+	uint32_t		tail;
 	uint32_t		watchdog_timer;
 	union ixgbe_adv_tx_desc	*tx_base;
 	struct ixgbe_tx_buf	*tx_buffers;
@@ -194,6 +195,7 @@ struct ix_rxring {
 	struct ix_softc		*sc;
 	struct ifiqueue		*ifiq;
 	uint32_t		me;
+	uint32_t		tail;
 	union ixgbe_adv_rx_desc	*rx_base;
 	struct ixgbe_dma_alloc	rxdma;
 #if 0
@@ -244,6 +246,7 @@ struct ix_softc {
 	uint16_t		num_segs;
 	uint32_t		link_speed;
 	bool			link_up;
+	bool			link_enabled;
 	uint32_t		linkvec;
 	struct rwlock		sfflock;
 
-- 
2.20.1