From 186cbc3a3b56f546f23ecca4741c1ef97dac6cdb Mon Sep 17 00:00:00 2001 From: jsg Date: Mon, 27 Mar 2023 04:19:29 +0000 Subject: [PATCH] drm/amd: Fix initialization for nbio 7.5.1 From Mario Limonciello 749b249d1ba94d976b5f1e32fcd5059b45bc4c4a in linux-6.1.y/6.1.16 65a24000808f70ac69bd2a96381fa0c7341f20c0 in mainline linux --- sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c b/sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c index 31776b12e4c..4b0d563c652 100644 --- a/sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c +++ b/sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c @@ -382,6 +382,11 @@ static void nbio_v7_2_init_registers(struct amdgpu_device *adev) if (def != data) WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_MST_CTRL_3), data); break; + case IP_VERSION(7, 5, 1): + data = RREG32_SOC15(NBIO, 0, regRCC_DEV2_EPF0_STRAP2); + data &= ~RCC_DEV2_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV2_F0_MASK; + WREG32_SOC15(NBIO, 0, regRCC_DEV2_EPF0_STRAP2, data); + fallthrough; default: def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CONFIG_CNTL)); data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, -- 2.20.1