From 1360042240f776a0bf1fe9c185fcd09ffc8deeb0 Mon Sep 17 00:00:00 2001
From: patrick <patrick@openbsd.org>
Date: Mon, 15 Jul 2024 09:54:38 +0000
Subject: [PATCH] Add RK3588 eMMC clocks and resets.

ok dlg@
---
 sys/dev/fdt/rkclock.c        | 36 +++++++++++++++++++++++++++++++++++-
 sys/dev/fdt/rkclock_clocks.h | 10 ++++++++++
 2 files changed, 45 insertions(+), 1 deletion(-)

diff --git a/sys/dev/fdt/rkclock.c b/sys/dev/fdt/rkclock.c
index 568601faf0f..8721604f774 100644
--- a/sys/dev/fdt/rkclock.c
+++ b/sys/dev/fdt/rkclock.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: rkclock.c,v 1.89 2024/06/11 09:15:33 kettenis Exp $	*/
+/*	$OpenBSD: rkclock.c,v 1.90 2024/07/15 09:54:38 patrick Exp $	*/
 /*
  * Copyright (c) 2017, 2018 Mark Kettenis <kettenis@openbsd.org>
  *
@@ -4217,6 +4217,20 @@ const struct rkclock rk3588_clocks[] = {
 		{ RK3588_CLK_GPU_SRC },
 		SET_PARENT
 	},
+	{
+		RK3588_CCLK_EMMC, RK3588_CRU_CLKSEL_CON(77),
+		SEL(15, 14), DIV(13, 8),
+		{ RK3588_PLL_GPLL, RK3588_PLL_CPLL, RK3588_XIN24M }
+	},
+	{
+		RK3588_BCLK_EMMC, RK3588_CRU_CLKSEL_CON(78),
+		SEL(5, 5), DIV(4, 0),
+		{ RK3588_PLL_GPLL, RK3588_PLL_CPLL }
+	},
+	{
+		RK3588_TMCLK_EMMC, 0, 0, 0,
+		{ RK3588_XIN24M }
+	},
 	{
 		RK3588_CLK_GMAC_125M, RK3588_CRU_CLKSEL_CON(83),
 		SEL(15, 15), DIV(14, 8),
@@ -4567,6 +4581,26 @@ rk3588_reset(void *cookie, uint32_t *cells, int on)
 		reg = RK3588_CRU_SOFTRST_CON(12);
 		bit = 1;
 		break;
+	case RK3588_SRST_H_EMMC:
+		reg = RK3588_CRU_SOFTRST_CON(31);
+		bit = 4;
+		break;
+	case RK3588_SRST_A_EMMC:
+		reg = RK3588_CRU_SOFTRST_CON(31);
+		bit = 5;
+		break;
+	case RK3588_SRST_C_EMMC:
+		reg = RK3588_CRU_SOFTRST_CON(31);
+		bit = 6;
+		break;
+	case RK3588_SRST_B_EMMC:
+		reg = RK3588_CRU_SOFTRST_CON(31);
+		bit = 7;
+		break;
+	case RK3588_SRST_T_EMMC:
+		reg = RK3588_CRU_SOFTRST_CON(31);
+		bit = 8;
+		break;
 	case RK3588_SRST_A_GMAC0:
 		reg = RK3588_CRU_SOFTRST_CON(32);
 		bit = 10;
diff --git a/sys/dev/fdt/rkclock_clocks.h b/sys/dev/fdt/rkclock_clocks.h
index c7707355cac..927b105ada2 100644
--- a/sys/dev/fdt/rkclock_clocks.h
+++ b/sys/dev/fdt/rkclock_clocks.h
@@ -480,6 +480,11 @@
 #define RK3588_ACLK_LOW_TOP_ROOT	258
 #define RK3588_CLK_GPU_SRC		261
 #define RK3588_CLK_GPU			262
+#define RK3588_HCLK_EMMC		298
+#define RK3588_ACLK_EMMC		299
+#define RK3588_CCLK_EMMC		300
+#define RK3588_BCLK_EMMC		301
+#define RK3588_TMCLK_EMMC		302
 #define RK3588_CLK_GMAC_125M		310
 #define RK3588_CCLK_SRC_SDIO		395
 #define RK3588_ACLK_VOP_ROOT		600
@@ -513,6 +518,11 @@
 
 #define RK3588_SRST_P_TSADC		86
 #define RK3588_SRST_TSADC		87
+#define RK3588_SRST_H_EMMC		278
+#define RK3588_SRST_A_EMMC		279
+#define RK3588_SRST_C_EMMC		280
+#define RK3588_SRST_B_EMMC		281
+#define RK3588_SRST_T_EMMC		282
 #define RK3588_SRST_A_GMAC0		291
 #define RK3588_SRST_A_GMAC1		292
 #define RK3588_SRST_PCIE0_POWER_UP	294
-- 
2.20.1