From 0f7a8b19251c70879caea275c43d9ba7db7d83b8 Mon Sep 17 00:00:00 2001 From: jsg Date: Mon, 9 Sep 2024 08:29:45 +0000 Subject: [PATCH] drm/amdgpu/pm: Check the return value of smum_send_msg_to_smc From Ma Jun a2f2beaba783e5e99b05bb455b701257e6f1fa37 in linux-6.6.y/6.6.50 579f0c21baec9e7506b6bb3f60f0a9b6d07693b4 in mainline linux --- sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c b/sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c index 813621b6d36..40d5f00b1e8 100644 --- a/sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c +++ b/sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c @@ -1036,7 +1036,9 @@ static int smu10_print_clock_levels(struct pp_hwmgr *hwmgr, switch (type) { case PP_SCLK: - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetGfxclkFrequency, &now); + ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetGfxclkFrequency, &now); + if (ret) + return ret; /* driver only know min/max gfx_clk, Add level 1 for all other gfx clks */ if (now == data->gfx_max_freq_limit/100) @@ -1057,7 +1059,9 @@ static int smu10_print_clock_levels(struct pp_hwmgr *hwmgr, i == 2 ? "*" : ""); break; case PP_MCLK: - smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetFclkFrequency, &now); + ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetFclkFrequency, &now); + if (ret) + return ret; for (i = 0; i < mclk_table->count; i++) size += snprintf(buf + size, PAGE_SIZE - size, "%d: %uMhz %s\n", -- 2.20.1