From 0e80c72c460771685457d7e50cfd2f7163f7ec82 Mon Sep 17 00:00:00 2001 From: jsg Date: Mon, 27 Mar 2023 04:07:06 +0000 Subject: [PATCH] drm/amd/display: fix FCLK pstate change underflow From Vladimir Stempen 4bdfa48d74649898468a0bf5c8b8a48dded77b4a in linux-6.1.y/6.1.16 972243f973eb0821084e5833d5f7f4ed025f42da in mainline linux --- sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c b/sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c index d90216d2fe3..04cc96e7009 100644 --- a/sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c +++ b/sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c @@ -1963,6 +1963,10 @@ void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context, */ context->bw_ctx.bw.dcn.watermarks.a = context->bw_ctx.bw.dcn.watermarks.c; context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 0; + /* Calculate FCLK p-state change watermark based on FCLK pstate change latency in case + * UCLK p-state is not supported, to avoid underflow in case FCLK pstate is supported + */ + context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; } else { /* Set A: * All clocks min. -- 2.20.1