From 0aed8ed9bbd3b447d0cf5654b8a331c0affce43d Mon Sep 17 00:00:00 2001 From: brynet Date: Wed, 1 Aug 2018 20:33:53 +0000 Subject: [PATCH] On AMD CPUs, If the LFENCE serialization MSR bit is already set, then we don't need to uncondtionally set it. Worksaround a suspected bug in newer Linux KVM, which may trigger a #GP fault on writes to this MSR. ok mlarkin@ --- sys/arch/amd64/amd64/identcpu.c | 8 +++++--- sys/arch/i386/i386/machdep.c | 8 +++++--- 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/sys/arch/amd64/amd64/identcpu.c b/sys/arch/amd64/amd64/identcpu.c index 6e0aee2b401..4947ce0a79c 100644 --- a/sys/arch/amd64/amd64/identcpu.c +++ b/sys/arch/amd64/amd64/identcpu.c @@ -1,4 +1,4 @@ -/* $OpenBSD: identcpu.c,v 1.103 2018/07/23 23:25:02 brynet Exp $ */ +/* $OpenBSD: identcpu.c,v 1.104 2018/08/01 20:33:53 brynet Exp $ */ /* $NetBSD: identcpu.c,v 1.1 2003/04/26 18:39:28 fvdl Exp $ */ /* @@ -656,8 +656,10 @@ identifycpu(struct cpu_info *ci) uint64_t msr; msr = rdmsr(MSR_DE_CFG); - msr |= DE_CFG_SERIALIZE_LFENCE; - wrmsr(MSR_DE_CFG, msr); + if ((msr & DE_CFG_SERIALIZE_LFENCE) == 0) { + msr |= DE_CFG_SERIALIZE_LFENCE; + wrmsr(MSR_DE_CFG, msr); + } } } diff --git a/sys/arch/i386/i386/machdep.c b/sys/arch/i386/i386/machdep.c index a47f5e7037a..cf18a1e85b5 100644 --- a/sys/arch/i386/i386/machdep.c +++ b/sys/arch/i386/i386/machdep.c @@ -1,4 +1,4 @@ -/* $OpenBSD: machdep.c,v 1.622 2018/07/30 14:19:12 kettenis Exp $ */ +/* $OpenBSD: machdep.c,v 1.623 2018/08/01 20:33:53 brynet Exp $ */ /* $NetBSD: machdep.c,v 1.214 1996/11/10 03:16:17 thorpej Exp $ */ /*- @@ -2038,8 +2038,10 @@ identifycpu(struct cpu_info *ci) uint64_t msr; msr = rdmsr(MSR_DE_CFG); - msr |= DE_CFG_SERIALIZE_LFENCE; - wrmsr(MSR_DE_CFG, msr); + if ((msr & DE_CFG_SERIALIZE_LFENCE) == 0) { + msr |= DE_CFG_SERIALIZE_LFENCE; + wrmsr(MSR_DE_CFG, msr); + } } } -- 2.20.1