From 09da619ceccb4baa1073d8b57547f10eb53f705a Mon Sep 17 00:00:00 2001 From: kettenis Date: Wed, 29 Nov 2023 23:32:16 +0000 Subject: [PATCH] Fix unwanted sign-extension of ID register masks. Sign-extension of the GPI feature mask caused misdetection of the GPI feature when some other feature was present that was advertised in the upper 32 bits of the same ID register. Resulting in a crash as soon as the pmap code tried to set the PAC keys. Fix suggested by Marc Zyngier who found and debugged the problem. ok jsg@, deraadt@ --- sys/arch/arm64/include/armreg.h | 306 ++++++++++++++++---------------- 1 file changed, 153 insertions(+), 153 deletions(-) diff --git a/sys/arch/arm64/include/armreg.h b/sys/arch/arm64/include/armreg.h index 94e76ff28de..91d2f402a89 100644 --- a/sys/arch/arm64/include/armreg.h +++ b/sys/arch/arm64/include/armreg.h @@ -1,4 +1,4 @@ -/* $OpenBSD: armreg.h,v 1.29 2023/06/10 19:30:48 kettenis Exp $ */ +/* $OpenBSD: armreg.h,v 1.30 2023/11/29 23:32:16 kettenis Exp $ */ /*- * Copyright (c) 2013, 2014 Andrew Turner * Copyright (c) 2015 The FreeBSD Foundation @@ -218,69 +218,69 @@ /* ID_AA64DFR0_EL1 */ #define ID_AA64DFR0_MASK 0x00000000f0f0ffffUL #define ID_AA64DFR0_DEBUG_VER_SHIFT 0 -#define ID_AA64DFR0_DEBUG_VER_MASK (0xf << ID_AA64DFR0_DEBUG_VER_SHIFT) +#define ID_AA64DFR0_DEBUG_VER_MASK (0xfULL << ID_AA64DFR0_DEBUG_VER_SHIFT) #define ID_AA64DFR0_DEBUG_VER(x) ((x) & ID_AA64DFR0_DEBUG_VER_MASK) -#define ID_AA64DFR0_DEBUG_VER_8 (0x6 << ID_AA64DFR0_DEBUG_VER_SHIFT) -#define ID_AA64DFR0_DEBUG_VER_8_VHE (0x7 << ID_AA64DFR0_DEBUG_VER_SHIFT) +#define ID_AA64DFR0_DEBUG_VER_8 (0x6ULL << ID_AA64DFR0_DEBUG_VER_SHIFT) +#define ID_AA64DFR0_DEBUG_VER_8_VHE (0x7ULL << ID_AA64DFR0_DEBUG_VER_SHIFT) #define ID_AA64DFR0_TRACE_VER_SHIFT 4 -#define ID_AA64DFR0_TRACE_VER_MASK (0xf << ID_AA64DFR0_TRACE_VER_SHIFT) +#define ID_AA64DFR0_TRACE_VER_MASK (0xfULL << ID_AA64DFR0_TRACE_VER_SHIFT) #define ID_AA64DFR0_TRACE_VER(x) ((x) & ID_AA64DFR0_TRACE_VER_MASK) -#define ID_AA64DFR0_TRACE_VER_NONE (0x0 << ID_AA64DFR0_TRACE_VER_SHIFT) -#define ID_AA64DFR0_TRACE_VER_IMPL (0x1 << ID_AA64DFR0_TRACE_VER_SHIFT) +#define ID_AA64DFR0_TRACE_VER_NONE (0x0ULL << ID_AA64DFR0_TRACE_VER_SHIFT) +#define ID_AA64DFR0_TRACE_VER_IMPL (0x1ULL << ID_AA64DFR0_TRACE_VER_SHIFT) #define ID_AA64DFR0_PMU_VER_SHIFT 8 -#define ID_AA64DFR0_PMU_VER_MASK (0xf << ID_AA64DFR0_PMU_VER_SHIFT) +#define ID_AA64DFR0_PMU_VER_MASK (0xfULL << ID_AA64DFR0_PMU_VER_SHIFT) #define ID_AA64DFR0_PMU_VER(x) ((x) & ID_AA64DFR0_PMU_VER_MASK) -#define ID_AA64DFR0_PMU_VER_NONE (0x0 << ID_AA64DFR0_PMU_VER_SHIFT) -#define ID_AA64DFR0_PMU_VER_3 (0x1 << ID_AA64DFR0_PMU_VER_SHIFT) -#define ID_AA64DFR0_PMU_VER_3_1 (0x4 << ID_AA64DFR0_PMU_VER_SHIFT) -#define ID_AA64DFR0_PMU_VER_IMPL (0xf << ID_AA64DFR0_PMU_VER_SHIFT) +#define ID_AA64DFR0_PMU_VER_NONE (0x0ULL << ID_AA64DFR0_PMU_VER_SHIFT) +#define ID_AA64DFR0_PMU_VER_3 (0x1ULL << ID_AA64DFR0_PMU_VER_SHIFT) +#define ID_AA64DFR0_PMU_VER_3_1 (0x4ULL << ID_AA64DFR0_PMU_VER_SHIFT) +#define ID_AA64DFR0_PMU_VER_IMPL (0xfULL << ID_AA64DFR0_PMU_VER_SHIFT) #define ID_AA64DFR0_BRPS_SHIFT 12 -#define ID_AA64DFR0_BRPS_MASK (0xf << ID_AA64DFR0_BRPS_SHIFT) +#define ID_AA64DFR0_BRPS_MASK (0xfULL << ID_AA64DFR0_BRPS_SHIFT) #define ID_AA64DFR0_BRPS(x) \ ((((x) >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) + 1) #define ID_AA64DFR0_WRPS_SHIFT 20 -#define ID_AA64DFR0_WRPS_MASK (0xf << ID_AA64DFR0_WRPS_SHIFT) +#define ID_AA64DFR0_WRPS_MASK (0xfULL << ID_AA64DFR0_WRPS_SHIFT) #define ID_AA64DFR0_WRPS(x) \ ((((x) >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) + 1) #define ID_AA64DFR0_CTX_CMPS_SHIFT 28 -#define ID_AA64DFR0_CTX_CMPS_MASK (0xf << ID_AA64DFR0_CTX_CMPS_SHIFT) +#define ID_AA64DFR0_CTX_CMPS_MASK (0xfULL << ID_AA64DFR0_CTX_CMPS_SHIFT) #define ID_AA64DFR0_CTX_CMPS(x) \ ((((x) >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) + 1) /* ID_AA64ISAR0_EL1 */ #define ID_AA64ISAR0_MASK 0xfffffffff0fffff0ULL #define ID_AA64ISAR0_AES_SHIFT 4 -#define ID_AA64ISAR0_AES_MASK (0xf << ID_AA64ISAR0_AES_SHIFT) +#define ID_AA64ISAR0_AES_MASK (0xfULL << ID_AA64ISAR0_AES_SHIFT) #define ID_AA64ISAR0_AES(x) ((x) & ID_AA64ISAR0_AES_MASK) -#define ID_AA64ISAR0_AES_NONE (0x0 << ID_AA64ISAR0_AES_SHIFT) -#define ID_AA64ISAR0_AES_BASE (0x1 << ID_AA64ISAR0_AES_SHIFT) -#define ID_AA64ISAR0_AES_PMULL (0x2 << ID_AA64ISAR0_AES_SHIFT) +#define ID_AA64ISAR0_AES_NONE (0x0ULL << ID_AA64ISAR0_AES_SHIFT) +#define ID_AA64ISAR0_AES_BASE (0x1ULL << ID_AA64ISAR0_AES_SHIFT) +#define ID_AA64ISAR0_AES_PMULL (0x2ULL << ID_AA64ISAR0_AES_SHIFT) #define ID_AA64ISAR0_SHA1_SHIFT 8 -#define ID_AA64ISAR0_SHA1_MASK (0xf << ID_AA64ISAR0_SHA1_SHIFT) +#define ID_AA64ISAR0_SHA1_MASK (0xfULL << ID_AA64ISAR0_SHA1_SHIFT) #define ID_AA64ISAR0_SHA1(x) ((x) & ID_AA64ISAR0_SHA1_MASK) -#define ID_AA64ISAR0_SHA1_NONE (0x0 << ID_AA64ISAR0_SHA1_SHIFT) -#define ID_AA64ISAR0_SHA1_BASE (0x1 << ID_AA64ISAR0_SHA1_SHIFT) +#define ID_AA64ISAR0_SHA1_NONE (0x0ULL << ID_AA64ISAR0_SHA1_SHIFT) +#define ID_AA64ISAR0_SHA1_BASE (0x1ULL << ID_AA64ISAR0_SHA1_SHIFT) #define ID_AA64ISAR0_SHA2_SHIFT 12 -#define ID_AA64ISAR0_SHA2_MASK (0xf << ID_AA64ISAR0_SHA2_SHIFT) +#define ID_AA64ISAR0_SHA2_MASK (0xfULL << ID_AA64ISAR0_SHA2_SHIFT) #define ID_AA64ISAR0_SHA2(x) ((x) & ID_AA64ISAR0_SHA2_MASK) -#define ID_AA64ISAR0_SHA2_NONE (0x0 << ID_AA64ISAR0_SHA2_SHIFT) -#define ID_AA64ISAR0_SHA2_BASE (0x1 << ID_AA64ISAR0_SHA2_SHIFT) -#define ID_AA64ISAR0_SHA2_512 (0x2 << ID_AA64ISAR0_SHA2_SHIFT) +#define ID_AA64ISAR0_SHA2_NONE (0x0ULL << ID_AA64ISAR0_SHA2_SHIFT) +#define ID_AA64ISAR0_SHA2_BASE (0x1ULL << ID_AA64ISAR0_SHA2_SHIFT) +#define ID_AA64ISAR0_SHA2_512 (0x2ULL << ID_AA64ISAR0_SHA2_SHIFT) #define ID_AA64ISAR0_CRC32_SHIFT 16 -#define ID_AA64ISAR0_CRC32_MASK (0xf << ID_AA64ISAR0_CRC32_SHIFT) +#define ID_AA64ISAR0_CRC32_MASK (0xfULL << ID_AA64ISAR0_CRC32_SHIFT) #define ID_AA64ISAR0_CRC32(x) ((x) & ID_AA64ISAR0_CRC32_MASK) -#define ID_AA64ISAR0_CRC32_NONE (0x0 << ID_AA64ISAR0_CRC32_SHIFT) -#define ID_AA64ISAR0_CRC32_BASE (0x1 << ID_AA64ISAR0_CRC32_SHIFT) +#define ID_AA64ISAR0_CRC32_NONE (0x0ULL << ID_AA64ISAR0_CRC32_SHIFT) +#define ID_AA64ISAR0_CRC32_BASE (0x1ULL << ID_AA64ISAR0_CRC32_SHIFT) #define ID_AA64ISAR0_ATOMIC_SHIFT 20 -#define ID_AA64ISAR0_ATOMIC_MASK (0xf << ID_AA64ISAR0_ATOMIC_SHIFT) +#define ID_AA64ISAR0_ATOMIC_MASK (0xfULL << ID_AA64ISAR0_ATOMIC_SHIFT) #define ID_AA64ISAR0_ATOMIC(x) ((x) & ID_AA64ISAR0_ATOMIC_MASK) -#define ID_AA64ISAR0_ATOMIC_NONE (0x0 << ID_AA64ISAR0_ATOMIC_SHIFT) -#define ID_AA64ISAR0_ATOMIC_IMPL (0x2 << ID_AA64ISAR0_ATOMIC_SHIFT) +#define ID_AA64ISAR0_ATOMIC_NONE (0x0ULL << ID_AA64ISAR0_ATOMIC_SHIFT) +#define ID_AA64ISAR0_ATOMIC_IMPL (0x2ULL << ID_AA64ISAR0_ATOMIC_SHIFT) #define ID_AA64ISAR0_RDM_SHIFT 28 -#define ID_AA64ISAR0_RDM_MASK (0xf << ID_AA64ISAR0_RDM_SHIFT) +#define ID_AA64ISAR0_RDM_MASK (0xfULL << ID_AA64ISAR0_RDM_SHIFT) #define ID_AA64ISAR0_RDM(x) ((x) & ID_AA64ISAR0_RDM_MASK) -#define ID_AA64ISAR0_RDM_NONE (0x0 << ID_AA64ISAR0_RDM_SHIFT) -#define ID_AA64ISAR0_RDM_IMPL (0x1 << ID_AA64ISAR0_RDM_SHIFT) +#define ID_AA64ISAR0_RDM_NONE (0x0ULL << ID_AA64ISAR0_RDM_SHIFT) +#define ID_AA64ISAR0_RDM_IMPL (0x1ULL << ID_AA64ISAR0_RDM_SHIFT) #define ID_AA64ISAR0_SHA3_SHIFT 32 #define ID_AA64ISAR0_SHA3_MASK (0xfULL << ID_AA64ISAR0_SHA3_SHIFT) #define ID_AA64ISAR0_SHA3(x) ((x) & ID_AA64ISAR0_SHA3_MASK) @@ -327,48 +327,48 @@ /* ID_AA64ISAR1_EL1 */ #define ID_AA64ISAR1_MASK 0x00000fffffffffffULL #define ID_AA64ISAR1_DPB_SHIFT 0 -#define ID_AA64ISAR1_DPB_MASK (0xf << ID_AA64ISAR1_DPB_SHIFT) +#define ID_AA64ISAR1_DPB_MASK (0xfULL << ID_AA64ISAR1_DPB_SHIFT) #define ID_AA64ISAR1_DPB(x) ((x) & ID_AA64ISAR1_DPB_MASK) -#define ID_AA64ISAR1_DPB_NONE (0x0 << ID_AA64ISAR1_DPB_SHIFT) -#define ID_AA64ISAR1_DPB_IMPL (0x1 << ID_AA64ISAR1_DPB_SHIFT) +#define ID_AA64ISAR1_DPB_NONE (0x0ULL << ID_AA64ISAR1_DPB_SHIFT) +#define ID_AA64ISAR1_DPB_IMPL (0x1ULL << ID_AA64ISAR1_DPB_SHIFT) #define ID_AA64ISAR1_APA_SHIFT 4 -#define ID_AA64ISAR1_APA_MASK (0xf << ID_AA64ISAR1_APA_SHIFT) +#define ID_AA64ISAR1_APA_MASK (0xfULL << ID_AA64ISAR1_APA_SHIFT) #define ID_AA64ISAR1_APA(x) ((x) & ID_AA64ISAR1_APA_MASK) -#define ID_AA64ISAR1_APA_NONE (0x0 << ID_AA64ISAR1_APA_SHIFT) -#define ID_AA64ISAR1_APA_BASE (0x1 << ID_AA64ISAR1_APA_SHIFT) -#define ID_AA64ISAR1_APA_PAC (0x2 << ID_AA64ISAR1_APA_SHIFT) +#define ID_AA64ISAR1_APA_NONE (0x0ULL << ID_AA64ISAR1_APA_SHIFT) +#define ID_AA64ISAR1_APA_BASE (0x1ULL << ID_AA64ISAR1_APA_SHIFT) +#define ID_AA64ISAR1_APA_PAC (0x2ULL << ID_AA64ISAR1_APA_SHIFT) #define ID_AA64ISAR1_API_SHIFT 8 -#define ID_AA64ISAR1_API_MASK (0xf << ID_AA64ISAR1_API_SHIFT) +#define ID_AA64ISAR1_API_MASK (0xfULL << ID_AA64ISAR1_API_SHIFT) #define ID_AA64ISAR1_API(x) ((x) & ID_AA64ISAR1_API_MASK) -#define ID_AA64ISAR1_API_NONE (0x0 << ID_AA64ISAR1_API_SHIFT) -#define ID_AA64ISAR1_API_BASE (0x1 << ID_AA64ISAR1_API_SHIFT) -#define ID_AA64ISAR1_API_PAC (0x2 << ID_AA64ISAR1_API_SHIFT) +#define ID_AA64ISAR1_API_NONE (0x0ULL << ID_AA64ISAR1_API_SHIFT) +#define ID_AA64ISAR1_API_BASE (0x1ULL << ID_AA64ISAR1_API_SHIFT) +#define ID_AA64ISAR1_API_PAC (0x2ULL << ID_AA64ISAR1_API_SHIFT) #define ID_AA64ISAR1_JSCVT_SHIFT 12 -#define ID_AA64ISAR1_JSCVT_MASK (0xf << ID_AA64ISAR1_JSCVT_SHIFT) +#define ID_AA64ISAR1_JSCVT_MASK (0xfULL << ID_AA64ISAR1_JSCVT_SHIFT) #define ID_AA64ISAR1_JSCVT(x) ((x) & ID_AA64ISAR1_JSCVT_MASK) -#define ID_AA64ISAR1_JSCVT_NONE (0x0 << ID_AA64ISAR1_JSCVT_SHIFT) -#define ID_AA64ISAR1_JSCVT_IMPL (0x1 << ID_AA64ISAR1_JSCVT_SHIFT) +#define ID_AA64ISAR1_JSCVT_NONE (0x0ULL << ID_AA64ISAR1_JSCVT_SHIFT) +#define ID_AA64ISAR1_JSCVT_IMPL (0x1ULL << ID_AA64ISAR1_JSCVT_SHIFT) #define ID_AA64ISAR1_FCMA_SHIFT 16 -#define ID_AA64ISAR1_FCMA_MASK (0xf << ID_AA64ISAR1_FCMA_SHIFT) +#define ID_AA64ISAR1_FCMA_MASK (0xfULL << ID_AA64ISAR1_FCMA_SHIFT) #define ID_AA64ISAR1_FCMA(x) ((x) & ID_AA64ISAR1_FCMA_MASK) -#define ID_AA64ISAR1_FCMA_NONE (0x0 << ID_AA64ISAR1_FCMA_SHIFT) -#define ID_AA64ISAR1_FCMA_IMPL (0x1 << ID_AA64ISAR1_FCMA_SHIFT) +#define ID_AA64ISAR1_FCMA_NONE (0x0ULL << ID_AA64ISAR1_FCMA_SHIFT) +#define ID_AA64ISAR1_FCMA_IMPL (0x1ULL << ID_AA64ISAR1_FCMA_SHIFT) #define ID_AA64ISAR1_LRCPC_SHIFT 20 -#define ID_AA64ISAR1_LRCPC_MASK (0xf << ID_AA64ISAR1_LRCPC_SHIFT) +#define ID_AA64ISAR1_LRCPC_MASK (0xfULL << ID_AA64ISAR1_LRCPC_SHIFT) #define ID_AA64ISAR1_LRCPC(x) ((x) & ID_AA64ISAR1_LRCPC_MASK) -#define ID_AA64ISAR1_LRCPC_NONE (0x0 << ID_AA64ISAR1_LRCPC_SHIFT) -#define ID_AA64ISAR1_LRCPC_BASE (0x1 << ID_AA64ISAR1_LRCPC_SHIFT) -#define ID_AA64ISAR1_LRCPC_LDAPUR (0x2 << ID_AA64ISAR1_LRCPC_SHIFT) +#define ID_AA64ISAR1_LRCPC_NONE (0x0ULL << ID_AA64ISAR1_LRCPC_SHIFT) +#define ID_AA64ISAR1_LRCPC_BASE (0x1ULL << ID_AA64ISAR1_LRCPC_SHIFT) +#define ID_AA64ISAR1_LRCPC_LDAPUR (0x2ULL << ID_AA64ISAR1_LRCPC_SHIFT) #define ID_AA64ISAR1_GPA_SHIFT 24 -#define ID_AA64ISAR1_GPA_MASK (0xf << ID_AA64ISAR1_GPA_SHIFT) +#define ID_AA64ISAR1_GPA_MASK (0xfULL << ID_AA64ISAR1_GPA_SHIFT) #define ID_AA64ISAR1_GPA(x) ((x) & ID_AA64ISAR1_GPA_MASK) -#define ID_AA64ISAR1_GPA_NONE (0x0 << ID_AA64ISAR1_GPA_SHIFT) -#define ID_AA64ISAR1_GPA_IMPL (0x1 << ID_AA64ISAR1_GPA_SHIFT) +#define ID_AA64ISAR1_GPA_NONE (0x0ULL << ID_AA64ISAR1_GPA_SHIFT) +#define ID_AA64ISAR1_GPA_IMPL (0x1ULL << ID_AA64ISAR1_GPA_SHIFT) #define ID_AA64ISAR1_GPI_SHIFT 28 -#define ID_AA64ISAR1_GPI_MASK (0xf << ID_AA64ISAR1_GPI_SHIFT) +#define ID_AA64ISAR1_GPI_MASK (0xfULL << ID_AA64ISAR1_GPI_SHIFT) #define ID_AA64ISAR1_GPI(x) ((x) & ID_AA64ISAR1_GPI_MASK) -#define ID_AA64ISAR1_GPI_NONE (0x0 << ID_AA64ISAR1_GPI_SHIFT) -#define ID_AA64ISAR1_GPI_IMPL (0x1 << ID_AA64ISAR1_GPI_SHIFT) +#define ID_AA64ISAR1_GPI_NONE (0x0ULL << ID_AA64ISAR1_GPI_SHIFT) +#define ID_AA64ISAR1_GPI_IMPL (0x1ULL << ID_AA64ISAR1_GPI_SHIFT) #define ID_AA64ISAR1_FRINTTS_SHIFT 32 #define ID_AA64ISAR1_FRINTTS_MASK (0xfULL << ID_AA64ISAR1_FRINTTS_SHIFT) #define ID_AA64ISAR1_FRINTTS(x) ((x) & ID_AA64ISAR1_FRINTTS_MASK) @@ -396,95 +396,95 @@ /* ID_AA64MMFR0_EL1 */ #define ID_AA64MMFR0_MASK 0x00000000ffffffffULL #define ID_AA64MMFR0_PA_RANGE_SHIFT 0 -#define ID_AA64MMFR0_PA_RANGE_MASK (0xf << ID_AA64MMFR0_PA_RANGE_SHIFT) +#define ID_AA64MMFR0_PA_RANGE_MASK (0xfULL << ID_AA64MMFR0_PA_RANGE_SHIFT) #define ID_AA64MMFR0_PA_RANGE(x) ((x) & ID_AA64MMFR0_PA_RANGE_MASK) -#define ID_AA64MMFR0_PA_RANGE_4G (0x0 << ID_AA64MMFR0_PA_RANGE_SHIFT) -#define ID_AA64MMFR0_PA_RANGE_64G (0x1 << ID_AA64MMFR0_PA_RANGE_SHIFT) -#define ID_AA64MMFR0_PA_RANGE_1T (0x2 << ID_AA64MMFR0_PA_RANGE_SHIFT) -#define ID_AA64MMFR0_PA_RANGE_4T (0x3 << ID_AA64MMFR0_PA_RANGE_SHIFT) -#define ID_AA64MMFR0_PA_RANGE_16T (0x4 << ID_AA64MMFR0_PA_RANGE_SHIFT) -#define ID_AA64MMFR0_PA_RANGE_256T (0x5 << ID_AA64MMFR0_PA_RANGE_SHIFT) +#define ID_AA64MMFR0_PA_RANGE_4G (0x0ULL << ID_AA64MMFR0_PA_RANGE_SHIFT) +#define ID_AA64MMFR0_PA_RANGE_64G (0x1ULL << ID_AA64MMFR0_PA_RANGE_SHIFT) +#define ID_AA64MMFR0_PA_RANGE_1T (0x2ULL << ID_AA64MMFR0_PA_RANGE_SHIFT) +#define ID_AA64MMFR0_PA_RANGE_4T (0x3ULL << ID_AA64MMFR0_PA_RANGE_SHIFT) +#define ID_AA64MMFR0_PA_RANGE_16T (0x4ULL << ID_AA64MMFR0_PA_RANGE_SHIFT) +#define ID_AA64MMFR0_PA_RANGE_256T (0x5ULL << ID_AA64MMFR0_PA_RANGE_SHIFT) #define ID_AA64MMFR0_ASID_BITS_SHIFT 4 -#define ID_AA64MMFR0_ASID_BITS_MASK (0xf << ID_AA64MMFR0_ASID_BITS_SHIFT) +#define ID_AA64MMFR0_ASID_BITS_MASK (0xfULL << ID_AA64MMFR0_ASID_BITS_SHIFT) #define ID_AA64MMFR0_ASID_BITS(x) ((x) & ID_AA64MMFR0_ASID_BITS_MASK) -#define ID_AA64MMFR0_ASID_BITS_8 (0x0 << ID_AA64MMFR0_ASID_BITS_SHIFT) -#define ID_AA64MMFR0_ASID_BITS_16 (0x2 << ID_AA64MMFR0_ASID_BITS_SHIFT) +#define ID_AA64MMFR0_ASID_BITS_8 (0x0ULL << ID_AA64MMFR0_ASID_BITS_SHIFT) +#define ID_AA64MMFR0_ASID_BITS_16 (0x2ULL << ID_AA64MMFR0_ASID_BITS_SHIFT) #define ID_AA64MMFR0_BIGEND_SHIFT 8 -#define ID_AA64MMFR0_BIGEND_MASK (0xf << ID_AA64MMFR0_BIGEND_SHIFT) +#define ID_AA64MMFR0_BIGEND_MASK (0xfULL << ID_AA64MMFR0_BIGEND_SHIFT) #define ID_AA64MMFR0_BIGEND(x) ((x) & ID_AA64MMFR0_BIGEND_MASK) -#define ID_AA64MMFR0_BIGEND_FIXED (0x0 << ID_AA64MMFR0_BIGEND_SHIFT) -#define ID_AA64MMFR0_BIGEND_MIXED (0x1 << ID_AA64MMFR0_BIGEND_SHIFT) +#define ID_AA64MMFR0_BIGEND_FIXED (0x0ULL << ID_AA64MMFR0_BIGEND_SHIFT) +#define ID_AA64MMFR0_BIGEND_MIXED (0x1ULL << ID_AA64MMFR0_BIGEND_SHIFT) #define ID_AA64MMFR0_S_NS_MEM_SHIFT 12 -#define ID_AA64MMFR0_S_NS_MEM_MASK (0xf << ID_AA64MMFR0_S_NS_MEM_SHIFT) +#define ID_AA64MMFR0_S_NS_MEM_MASK (0xfULL << ID_AA64MMFR0_S_NS_MEM_SHIFT) #define ID_AA64MMFR0_S_NS_MEM(x) ((x) & ID_AA64MMFR0_S_NS_MEM_MASK) -#define ID_AA64MMFR0_S_NS_MEM_NONE (0x0 << ID_AA64MMFR0_S_NS_MEM_SHIFT) -#define ID_AA64MMFR0_S_NS_MEM_DISTINCT (0x1 << ID_AA64MMFR0_S_NS_MEM_SHIFT) +#define ID_AA64MMFR0_S_NS_MEM_NONE (0x0ULL << ID_AA64MMFR0_S_NS_MEM_SHIFT) +#define ID_AA64MMFR0_S_NS_MEM_DISTINCT (0x1ULL << ID_AA64MMFR0_S_NS_MEM_SHIFT) #define ID_AA64MMFR0_BIGEND_EL0_SHIFT 16 -#define ID_AA64MMFR0_BIGEND_EL0_MASK (0xf << ID_AA64MMFR0_BIGEND_EL0_SHIFT) +#define ID_AA64MMFR0_BIGEND_EL0_MASK (0xfULL << ID_AA64MMFR0_BIGEND_EL0_SHIFT) #define ID_AA64MMFR0_BIGEND_EL0(x) ((x) & ID_AA64MMFR0_BIGEND_EL0_MASK) -#define ID_AA64MMFR0_BIGEND_EL0_FIXED (0x0 << ID_AA64MMFR0_BIGEND_EL0_SHIFT) -#define ID_AA64MMFR0_BIGEND_EL0_MIXED (0x1 << ID_AA64MMFR0_BIGEND_EL0_SHIFT) +#define ID_AA64MMFR0_BIGEND_EL0_FIXED (0x0ULL << ID_AA64MMFR0_BIGEND_EL0_SHIFT) +#define ID_AA64MMFR0_BIGEND_EL0_MIXED (0x1ULL << ID_AA64MMFR0_BIGEND_EL0_SHIFT) #define ID_AA64MMFR0_TGRAN16_SHIFT 20 -#define ID_AA64MMFR0_TGRAN16_MASK (0xf << ID_AA64MMFR0_TGRAN16_SHIFT) +#define ID_AA64MMFR0_TGRAN16_MASK (0xfULL << ID_AA64MMFR0_TGRAN16_SHIFT) #define ID_AA64MMFR0_TGRAN16(x) ((x) & ID_AA64MMFR0_TGRAN16_MASK) -#define ID_AA64MMFR0_TGRAN16_NONE (0x0 << ID_AA64MMFR0_TGRAN16_SHIFT) -#define ID_AA64MMFR0_TGRAN16_IMPL (0x1 << ID_AA64MMFR0_TGRAN16_SHIFT) +#define ID_AA64MMFR0_TGRAN16_NONE (0x0ULL << ID_AA64MMFR0_TGRAN16_SHIFT) +#define ID_AA64MMFR0_TGRAN16_IMPL (0x1ULL << ID_AA64MMFR0_TGRAN16_SHIFT) #define ID_AA64MMFR0_TGRAN64_SHIFT 24 -#define ID_AA64MMFR0_TGRAN64_MASK (0xf << ID_AA64MMFR0_TGRAN64_SHIFT) +#define ID_AA64MMFR0_TGRAN64_MASK (0xfULL << ID_AA64MMFR0_TGRAN64_SHIFT) #define ID_AA64MMFR0_TGRAN64(x) ((x) & ID_AA64MMFR0_TGRAN64_MASK) -#define ID_AA64MMFR0_TGRAN64_IMPL (0x0 << ID_AA64MMFR0_TGRAN64_SHIFT) -#define ID_AA64MMFR0_TGRAN64_NONE (0xf << ID_AA64MMFR0_TGRAN64_SHIFT) +#define ID_AA64MMFR0_TGRAN64_IMPL (0x0ULL << ID_AA64MMFR0_TGRAN64_SHIFT) +#define ID_AA64MMFR0_TGRAN64_NONE (0xfULL << ID_AA64MMFR0_TGRAN64_SHIFT) #define ID_AA64MMFR0_TGRAN4_SHIFT 28 -#define ID_AA64MMFR0_TGRAN4_MASK (0xf << ID_AA64MMFR0_TGRAN4_SHIFT) +#define ID_AA64MMFR0_TGRAN4_MASK (0xfULL << ID_AA64MMFR0_TGRAN4_SHIFT) #define ID_AA64MMFR0_TGRAN4(x) ((x) & ID_AA64MMFR0_TGRAN4_MASK) -#define ID_AA64MMFR0_TGRAN4_IMPL (0x0 << ID_AA64MMFR0_TGRAN4_SHIFT) -#define ID_AA64MMFR0_TGRAN4_NONE (0xf << ID_AA64MMFR0_TGRAN4_SHIFT) +#define ID_AA64MMFR0_TGRAN4_IMPL (0x0ULL << ID_AA64MMFR0_TGRAN4_SHIFT) +#define ID_AA64MMFR0_TGRAN4_NONE (0xfULL << ID_AA64MMFR0_TGRAN4_SHIFT) /* ID_AA64MMFR1_EL1 */ #define ID_AA64MMFR1_MASK 0xf0000000ffffffffULL #define ID_AA64MMFR1_HAFDBS_SHIFT 0 -#define ID_AA64MMFR1_HAFDBS_MASK (0xf << ID_AA64MMFR1_HAFDBS_SHIFT) +#define ID_AA64MMFR1_HAFDBS_MASK (0xfULL << ID_AA64MMFR1_HAFDBS_SHIFT) #define ID_AA64MMFR1_HAFDBS(x) ((x) & ID_AA64MMFR1_HAFDBS_MASK) -#define ID_AA64MMFR1_HAFDBS_NONE (0x0 << ID_AA64MMFR1_HAFDBS_SHIFT) -#define ID_AA64MMFR1_HAFDBS_AF (0x1 << ID_AA64MMFR1_HAFDBS_SHIFT) -#define ID_AA64MMFR1_HAFDBS_AF_DBS (0x2 << ID_AA64MMFR1_HAFDBS_SHIFT) +#define ID_AA64MMFR1_HAFDBS_NONE (0x0ULL << ID_AA64MMFR1_HAFDBS_SHIFT) +#define ID_AA64MMFR1_HAFDBS_AF (0x1ULL << ID_AA64MMFR1_HAFDBS_SHIFT) +#define ID_AA64MMFR1_HAFDBS_AF_DBS (0x2ULL << ID_AA64MMFR1_HAFDBS_SHIFT) #define ID_AA64MMFR1_VMIDBITS_SHIFT 4 -#define ID_AA64MMFR1_VMIDBITS_MASK (0xf << ID_AA64MMFR1_VMIDBITS_SHIFT) +#define ID_AA64MMFR1_VMIDBITS_MASK (0xfULL << ID_AA64MMFR1_VMIDBITS_SHIFT) #define ID_AA64MMFR1_VMIDBITS(x) ((x) & ID_AA64MMFR1_VMIDBITS_MASK) -#define ID_AA64MMFR1_VMIDBITS_8 (0x0 << ID_AA64MMFR1_VMIDBITS_SHIFT) -#define ID_AA64MMFR1_VMIDBITS_16 (0x2 << ID_AA64MMFR1_VMIDBITS_SHIFT) +#define ID_AA64MMFR1_VMIDBITS_8 (0x0ULL << ID_AA64MMFR1_VMIDBITS_SHIFT) +#define ID_AA64MMFR1_VMIDBITS_16 (0x2ULL << ID_AA64MMFR1_VMIDBITS_SHIFT) #define ID_AA64MMFR1_VH_SHIFT 8 -#define ID_AA64MMFR1_VH_MASK (0xf << ID_AA64MMFR1_VH_SHIFT) +#define ID_AA64MMFR1_VH_MASK (0xfULL << ID_AA64MMFR1_VH_SHIFT) #define ID_AA64MMFR1_VH(x) ((x) & ID_AA64MMFR1_VH_MASK) -#define ID_AA64MMFR1_VH_NONE (0x0 << ID_AA64MMFR1_VH_SHIFT) -#define ID_AA64MMFR1_VH_IMPL (0x1 << ID_AA64MMFR1_VH_SHIFT) +#define ID_AA64MMFR1_VH_NONE (0x0ULL << ID_AA64MMFR1_VH_SHIFT) +#define ID_AA64MMFR1_VH_IMPL (0x1ULL << ID_AA64MMFR1_VH_SHIFT) #define ID_AA64MMFR1_HPDS_SHIFT 12 -#define ID_AA64MMFR1_HPDS_MASK (0xf << ID_AA64MMFR1_HPDS_SHIFT) +#define ID_AA64MMFR1_HPDS_MASK (0xfULL << ID_AA64MMFR1_HPDS_SHIFT) #define ID_AA64MMFR1_HPDS(x) ((x) & ID_AA64MMFR1_HPDS_MASK) -#define ID_AA64MMFR1_HPDS_NONE (0x0 << ID_AA64MMFR1_HPDS_SHIFT) -#define ID_AA64MMFR1_HPDS_IMPL (0x1 << ID_AA64MMFR1_HPDS_SHIFT) +#define ID_AA64MMFR1_HPDS_NONE (0x0ULL << ID_AA64MMFR1_HPDS_SHIFT) +#define ID_AA64MMFR1_HPDS_IMPL (0x1ULL << ID_AA64MMFR1_HPDS_SHIFT) #define ID_AA64MMFR1_LO_SHIFT 16 -#define ID_AA64MMFR1_LO_MASK (0xf << ID_AA64MMFR1_LO_SHIFT) +#define ID_AA64MMFR1_LO_MASK (0xfULL << ID_AA64MMFR1_LO_SHIFT) #define ID_AA64MMFR1_LO(x) ((x) & ID_AA64MMFR1_LO_MASK) -#define ID_AA64MMFR1_LO_NONE (0x0 << ID_AA64MMFR1_LO_SHIFT) -#define ID_AA64MMFR1_LO_IMPL (0x1 << ID_AA64MMFR1_LO_SHIFT) +#define ID_AA64MMFR1_LO_NONE (0x0ULL << ID_AA64MMFR1_LO_SHIFT) +#define ID_AA64MMFR1_LO_IMPL (0x1ULL << ID_AA64MMFR1_LO_SHIFT) #define ID_AA64MMFR1_PAN_SHIFT 20 -#define ID_AA64MMFR1_PAN_MASK (0xf << ID_AA64MMFR1_PAN_SHIFT) +#define ID_AA64MMFR1_PAN_MASK (0xfULL << ID_AA64MMFR1_PAN_SHIFT) #define ID_AA64MMFR1_PAN(x) ((x) & ID_AA64MMFR1_PAN_MASK) -#define ID_AA64MMFR1_PAN_NONE (0x0 << ID_AA64MMFR1_PAN_SHIFT) -#define ID_AA64MMFR1_PAN_IMPL (0x1 << ID_AA64MMFR1_PAN_SHIFT) -#define ID_AA64MMFR1_PAN_ATS1E1 (0x2 << ID_AA64MMFR1_PAN_SHIFT) -#define ID_AA64MMFR1_PAN_EPAN (0x3 << ID_AA64MMFR1_PAN_SHIFT) +#define ID_AA64MMFR1_PAN_NONE (0x0ULL << ID_AA64MMFR1_PAN_SHIFT) +#define ID_AA64MMFR1_PAN_IMPL (0x1ULL << ID_AA64MMFR1_PAN_SHIFT) +#define ID_AA64MMFR1_PAN_ATS1E1 (0x2ULL << ID_AA64MMFR1_PAN_SHIFT) +#define ID_AA64MMFR1_PAN_EPAN (0x3ULL << ID_AA64MMFR1_PAN_SHIFT) #define ID_AA64MMFR1_SPECSEI_SHIFT 24 -#define ID_AA64MMFR1_SPECSEI_MASK (0xf << ID_AA64MMFR1_SPECSEI_SHIFT) +#define ID_AA64MMFR1_SPECSEI_MASK (0xfULL << ID_AA64MMFR1_SPECSEI_SHIFT) #define ID_AA64MMFR1_SPECSEI(x) ((x) & ID_AA64MMFR1_SPECSEI_MASK) -#define ID_AA64MMFR1_SPECSEI_NONE (0x0 << ID_AA64MMFR1_SPECSEI_SHIFT) -#define ID_AA64MMFR1_SPECSEI_IMPL (0x1 << ID_AA64MMFR1_SPECSEI_SHIFT) +#define ID_AA64MMFR1_SPECSEI_NONE (0x0ULL << ID_AA64MMFR1_SPECSEI_SHIFT) +#define ID_AA64MMFR1_SPECSEI_IMPL (0x1ULL << ID_AA64MMFR1_SPECSEI_SHIFT) #define ID_AA64MMFR1_XNX_SHIFT 28 -#define ID_AA64MMFR1_XNX_MASK (0xf << ID_AA64MMFR1_XNX_SHIFT) +#define ID_AA64MMFR1_XNX_MASK (0xfULL << ID_AA64MMFR1_XNX_SHIFT) #define ID_AA64MMFR1_XNX(x) ((x) & ID_AA64MMFR1_XNX_MASK) -#define ID_AA64MMFR1_XNX_NONE (0x0 << ID_AA64MMFR1_XNX_SHIFT) -#define ID_AA64MMFR1_XNX_IMPL (0x1 << ID_AA64MMFR1_XNX_SHIFT) +#define ID_AA64MMFR1_XNX_NONE (0x0ULL << ID_AA64MMFR1_XNX_SHIFT) +#define ID_AA64MMFR1_XNX_IMPL (0x1ULL << ID_AA64MMFR1_XNX_SHIFT) #define ID_AA64MMFR1_ECBHB_SHIFT 60 #define ID_AA64MMFR1_ECBHB_MASK (0xfULL << ID_AA64MMFR1_ECBHB_SHIFT) #define ID_AA64MMFR1_ECBHB(x) ((x) & ID_AA64MMFR1_ECBHB_MASK) @@ -494,43 +494,43 @@ /* ID_AA64PFR0_EL1 */ #define ID_AA64PFR0_MASK 0xff0fffffffffffffULL #define ID_AA64PFR0_EL0_SHIFT 0 -#define ID_AA64PFR0_EL0_MASK (0xf << ID_AA64PFR0_EL0_SHIFT) +#define ID_AA64PFR0_EL0_MASK (0xfULL << ID_AA64PFR0_EL0_SHIFT) #define ID_AA64PFR0_EL0(x) ((x) & ID_AA64PFR0_EL0_MASK) -#define ID_AA64PFR0_EL0_64 (1 << ID_AA64PFR0_EL0_SHIFT) -#define ID_AA64PFR0_EL0_64_32 (2 << ID_AA64PFR0_EL0_SHIFT) +#define ID_AA64PFR0_EL0_64 (0x1ULL << ID_AA64PFR0_EL0_SHIFT) +#define ID_AA64PFR0_EL0_64_32 (0x2ULL << ID_AA64PFR0_EL0_SHIFT) #define ID_AA64PFR0_EL1_SHIFT 4 -#define ID_AA64PFR0_EL1_MASK (0xf << ID_AA64PFR0_EL1_SHIFT) +#define ID_AA64PFR0_EL1_MASK (0xfULL << ID_AA64PFR0_EL1_SHIFT) #define ID_AA64PFR0_EL1(x) ((x) & ID_AA64PFR0_EL1_MASK) -#define ID_AA64PFR0_EL1_64 (1 << ID_AA64PFR0_EL1_SHIFT) -#define ID_AA64PFR0_EL1_64_32 (2 << ID_AA64PFR0_EL1_SHIFT) +#define ID_AA64PFR0_EL1_64 (0x1ULL << ID_AA64PFR0_EL1_SHIFT) +#define ID_AA64PFR0_EL1_64_32 (0x2ULL << ID_AA64PFR0_EL1_SHIFT) #define ID_AA64PFR0_EL2_SHIFT 8 -#define ID_AA64PFR0_EL2_MASK (0xf << ID_AA64PFR0_EL2_SHIFT) +#define ID_AA64PFR0_EL2_MASK (0xfULL << ID_AA64PFR0_EL2_SHIFT) #define ID_AA64PFR0_EL2(x) ((x) & ID_AA64PFR0_EL2_MASK) -#define ID_AA64PFR0_EL2_NONE (0 << ID_AA64PFR0_EL2_SHIFT) -#define ID_AA64PFR0_EL2_64 (1 << ID_AA64PFR0_EL2_SHIFT) -#define ID_AA64PFR0_EL2_64_32 (2 << ID_AA64PFR0_EL2_SHIFT) +#define ID_AA64PFR0_EL2_NONE (0x0ULL << ID_AA64PFR0_EL2_SHIFT) +#define ID_AA64PFR0_EL2_64 (0x1ULL << ID_AA64PFR0_EL2_SHIFT) +#define ID_AA64PFR0_EL2_64_32 (0x2ULL << ID_AA64PFR0_EL2_SHIFT) #define ID_AA64PFR0_EL3_SHIFT 12 -#define ID_AA64PFR0_EL3_MASK (0xf << ID_AA64PFR0_EL3_SHIFT) +#define ID_AA64PFR0_EL3_MASK (0xfULL << ID_AA64PFR0_EL3_SHIFT) #define ID_AA64PFR0_EL3(x) ((x) & ID_AA64PFR0_EL3_MASK) -#define ID_AA64PFR0_EL3_NONE (0 << ID_AA64PFR0_EL3_SHIFT) -#define ID_AA64PFR0_EL3_64 (1 << ID_AA64PFR0_EL3_SHIFT) -#define ID_AA64PFR0_EL3_64_32 (2 << ID_AA64PFR0_EL3_SHIFT) +#define ID_AA64PFR0_EL3_NONE (0x0ULL << ID_AA64PFR0_EL3_SHIFT) +#define ID_AA64PFR0_EL3_64 (0x1ULL << ID_AA64PFR0_EL3_SHIFT) +#define ID_AA64PFR0_EL3_64_32 (0x2ULL << ID_AA64PFR0_EL3_SHIFT) #define ID_AA64PFR0_FP_SHIFT 16 -#define ID_AA64PFR0_FP_MASK (0xf << ID_AA64PFR0_FP_SHIFT) +#define ID_AA64PFR0_FP_MASK (0xfULL << ID_AA64PFR0_FP_SHIFT) #define ID_AA64PFR0_FP(x) ((x) & ID_AA64PFR0_FP_MASK) -#define ID_AA64PFR0_FP_IMPL (0x0 << ID_AA64PFR0_FP_SHIFT) -#define ID_AA64PFR0_FP_NONE (0xf << ID_AA64PFR0_FP_SHIFT) +#define ID_AA64PFR0_FP_IMPL (0x0ULL << ID_AA64PFR0_FP_SHIFT) +#define ID_AA64PFR0_FP_NONE (0xfULL << ID_AA64PFR0_FP_SHIFT) #define ID_AA64PFR0_ADV_SIMD_SHIFT 20 -#define ID_AA64PFR0_ADV_SIMD_MASK (0xf << ID_AA64PFR0_ADV_SIMD_SHIFT) +#define ID_AA64PFR0_ADV_SIMD_MASK (0xfULL << ID_AA64PFR0_ADV_SIMD_SHIFT) #define ID_AA64PFR0_ADV_SIMD(x) ((x) & ID_AA64PFR0_ADV_SIMD_MASK) -#define ID_AA64PFR0_ADV_SIMD_IMPL (0x0 << ID_AA64PFR0_ADV_SIMD_SHIFT) -#define ID_AA64PFR0_ADV_SIMD_NONE (0xf << ID_AA64PFR0_ADV_SIMD_SHIFT) +#define ID_AA64PFR0_ADV_SIMD_IMPL (0x0ULL << ID_AA64PFR0_ADV_SIMD_SHIFT) +#define ID_AA64PFR0_ADV_SIMD_NONE (0xfULL << ID_AA64PFR0_ADV_SIMD_SHIFT) #define ID_AA64PFR0_GIC_BITS 0x4 /* Number of bits in GIC field */ #define ID_AA64PFR0_GIC_SHIFT 24 -#define ID_AA64PFR0_GIC_MASK (0xf << ID_AA64PFR0_GIC_SHIFT) +#define ID_AA64PFR0_GIC_MASK (0xfULL << ID_AA64PFR0_GIC_SHIFT) #define ID_AA64PFR0_GIC(x) ((x) & ID_AA64PFR0_GIC_MASK) -#define ID_AA64PFR0_GIC_CPUIF_NONE (0x0 << ID_AA64PFR0_GIC_SHIFT) -#define ID_AA64PFR0_GIC_CPUIF_EN (0x1 << ID_AA64PFR0_GIC_SHIFT) +#define ID_AA64PFR0_GIC_CPUIF_NONE (0x0ULL << ID_AA64PFR0_GIC_SHIFT) +#define ID_AA64PFR0_GIC_CPUIF_EN (0x1ULL << ID_AA64PFR0_GIC_SHIFT) #define ID_AA64PFR0_RAS_SHIFT 28 #define ID_AA64PFR0_RAS_MASK (0xfULL << ID_AA64PFR0_RAS_SHIFT) #define ID_AA64PFR0_RAS(x) ((x) & ID_AA64PFR0_RAS_MASK) @@ -578,26 +578,26 @@ /* ID_AA64PFR1_EL1 */ #define ID_AA64PFR1_MASK 0x000000000000ffffULL #define ID_AA64PFR1_BT_SHIFT 0 -#define ID_AA64PFR1_BT_MASK (0xf << ID_AA64PFR1_BT_SHIFT) +#define ID_AA64PFR1_BT_MASK (0xfULL << ID_AA64PFR1_BT_SHIFT) #define ID_AA64PFR1_BT(x) ((x) & ID_AA64PFR1_BT_MASK) -#define ID_AA64PFR1_BT_NONE (0 << ID_AA64PFR1_BT_SHIFT) -#define ID_AA64PFR1_BT_IMPL (1 << ID_AA64PFR1_BT_SHIFT) +#define ID_AA64PFR1_BT_NONE (0x0ULL << ID_AA64PFR1_BT_SHIFT) +#define ID_AA64PFR1_BT_IMPL (0x1ULL << ID_AA64PFR1_BT_SHIFT) #define ID_AA64PFR1_SBSS_SHIFT 4 -#define ID_AA64PFR1_SBSS_MASK (0xf << ID_AA64PFR1_SBSS_SHIFT) +#define ID_AA64PFR1_SBSS_MASK (0xfULL << ID_AA64PFR1_SBSS_SHIFT) #define ID_AA64PFR1_SBSS(x) ((x) & ID_AA64PFR1_SBSS_MASK) -#define ID_AA64PFR1_SBSS_NONE (0 << ID_AA64PFR1_SBSS_SHIFT) -#define ID_AA64PFR1_SBSS_PSTATE (1 << ID_AA64PFR1_SBSS_SHIFT) -#define ID_AA64PFR1_SBSS_PSTATE_MSR (2 << ID_AA64PFR1_SBSS_SHIFT) +#define ID_AA64PFR1_SBSS_NONE (0x0ULL << ID_AA64PFR1_SBSS_SHIFT) +#define ID_AA64PFR1_SBSS_PSTATE (0x1ULL << ID_AA64PFR1_SBSS_SHIFT) +#define ID_AA64PFR1_SBSS_PSTATE_MSR (0x2ULL << ID_AA64PFR1_SBSS_SHIFT) #define ID_AA64PFR1_MTE_SHIFT 8 -#define ID_AA64PFR1_MTE_MASK (0xf << ID_AA64PFR1_MTE_SHIFT) +#define ID_AA64PFR1_MTE_MASK (0xfULL << ID_AA64PFR1_MTE_SHIFT) #define ID_AA64PFR1_MTE(x) ((x) & ID_AA64PFR1_MTE_MASK) -#define ID_AA64PFR1_MTE_NONE (0 << ID_AA64PFR1_MTE_SHIFT) -#define ID_AA64PFR1_MTE_IMPL (1 << ID_AA64PFR1_MTE_SHIFT) +#define ID_AA64PFR1_MTE_NONE (0x0ULL << ID_AA64PFR1_MTE_SHIFT) +#define ID_AA64PFR1_MTE_IMPL (0x1ULL << ID_AA64PFR1_MTE_SHIFT) #define ID_AA64PFR1_RAS_FRAC_SHIFT 12 -#define ID_AA64PFR1_RAS_FRAC_MASK (0xf << ID_AA64PFR1_RAS_FRAC_SHIFT) +#define ID_AA64PFR1_RAS_FRAC_MASK (0xfULL << ID_AA64PFR1_RAS_FRAC_SHIFT) #define ID_AA64PFR1_RAS_FRAC(x) ((x) & ID_AA64PFR1_RAS_FRAC_MASK) -#define ID_AA64PFR1_RAS_FRAC_NONE (0 << ID_AA64PFR1_RAS_FRAC_SHIFT) -#define ID_AA64PFR1_RAS_FRAC_IMPL (1 << ID_AA64PFR1_RAS_FRAC_SHIFT) +#define ID_AA64PFR1_RAS_FRAC_NONE (0x0ULL << ID_AA64PFR1_RAS_FRAC_SHIFT) +#define ID_AA64PFR1_RAS_FRAC_IMPL (0x1ULL << ID_AA64PFR1_RAS_FRAC_SHIFT) /* MAIR_EL1 - Memory Attribute Indirection Register */ #define MAIR_ATTR_MASK(idx) (0xff << ((n)* 8)) -- 2.20.1